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? 2001 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as listed a t http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. ds003-2 (v2.5) april 2, 2001 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 1 architectural description virtex array the virtex user-programmable gate array, shown in figure 1 , comprises two major configurable elements: con- figurable logic blocks (clbs) and input/output blocks (iobs). ? clbs provide the functional elements for constructing logic iobs provide the interface between the package pins and the clbs clbs interconnect through a general routing matrix (grm). the grm comprises an array of routing switches located at the intersections of horizontal and vertical routing channels. each clb nests into a versablock? that also provides local routing resources to connect the clb to the grm. the versaring? i/o interface provides additional routing resources around the periphery of the device. this routing improves i/o routability and facilitates pin locking. the virtex architecture also includes the following circuits that connect to the grm. dedicated block memories of 4096 bits each clock dlls for clock-distribution delay compensation and clock domain control 3-state buffers (bufts) associated with each clb that drive dedicated segmentable horizontal routing resources values stored in static memory cells control the configurable logic elements and interconnect resources. these values load into the memory cells on power-up, and can reload if necessary to change the function of the device. input/output block the virtex iob, figure 2 , features selectio? inputs and outputs that support a wide variety of i/o signalling stan- dards, see ta b l e 1 . the three iob storage elements function either as edge-trig- gered d-type flip-flops or as level sensitive latches. each iob has a clock signal (clk) shared by the three flip-flops and independent clock enable signals for each flip-flop. in addition to the clk and ce control signals, the three flip-flops share a set/reset (sr). for each flip-flop, this sig- nal can be independently configured as a synchronous set, a synchronous reset, an asynchronous preset, or an asyn- chronous clear. the output buffer and all of the iob control signals have independent polarity controls. all pads are protected against damage from electrostatic discharge (esd) and from over-voltage transients. two forms of over-voltage protection are provided, one that per- mits 5 v compliance, and one that does not. for 5 v compli- ance, a zener-like structure connected to ground turns on when the output rises to approximately 6.5 v. when pci 3.3 v compliance is required, a conventional clamp diode is connected to the output supply voltage, v cco . optional pull-up and pull-down resistors and an optional weak-keeper circuit are attached to each pad. prior to con- figuration, all pins not involved in configuration are forced into their high-impedance state. the pull-down resistors and the weak-keeper circuits are inactive, but inputs can option- ally be pulled up. the activation of pull-up resistors prior to configuration is controlled on a global basis by the configuration mode pins. if the pull-up resistors are not activated, all the pins will float. consequently, external pull-up or pull-down resistors must be provided on pins required to be at a well-defined logic level prior to configuration. all virtex iobs support ieee 1149.1-compatible boundary scan testing. 0 virtex? 2.5 v field programmable gate arrays ds003-2 (v2.5) april 2, 2001 03 product specification r figure 1: virtex architecture overview vao_b.eps iobs iobs iobs iobs dll dll dll dll versaring versaring versaring versaring clbs brams brams
virtex ? 2.5 v field programmable gate arrays r module 2 of 4 www.xilinx.com ds003-2 (v2.5) april 2, 2001 2 1-800-255-7778 product specification figure 2: virtex input/output block (iob) obuft ibuf vref ds022_02_091300 sr clk ice oce o i iq t tce d ce q sr d ce q sr d ce q sr pad programmable delay weak keeper table 1: supported select i/o standards i/o standard input reference voltage (v ref ) output source voltag e (v cco ) board termination voltag e (v tt )5v tolerant lv t tl 2 ? 24 ma n/a 3.3 n/a yes lv c mo s2 n /a 2 .5 n / a ye s pci, 5 v n/a 3.3 n/a yes pci, 3.3 v n/a 3.3 n/a no gtl 0.8 n/a 1.2 no gtl+ 1.0 n/a 1.5 no hstl class i 0.75 1.5 0.75 no hstl class iii 0.9 1.5 1.5 no hstl class iv 0.9 1.5 1.5 no sstl3 class i &ii 1.5 3.3 1.5 no sstl2 class i & ii 1.25 2.5 1.25 no ctt 1.5 3.3 1.5 no agp 1.32 3.3 n/a no
virtex ? 2.5 v field programmable gate arrays r ds003-2 (v2.5) april 2, 2001 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 3 input path a buffer in the virtex iob input path routes the input signal either directly to internal logic or through an optional input flip-flop. an optional delay element at the d-input of this flip-flop elim- inates pad-to-pad hold time. the delay is matched to the internal clock-distribution delay of the fpga, and when used, assures that the pad-to-pad hold time is zero. each input buffer can be configured to conform to any of the low-voltage signalling standards supported. in some of these standards the input buffer utilizes a user-supplied threshold voltage, v ref . the need to supply v ref imposes constraints on which standards can used in close proximity to each other. see i/o banking , page 3 . there are optional pull-up and pull-down resistors at each input for use after configuration. their value is in the range 50 k w ? 100 k w . output path the output path includes a 3-state output buffer that drives the output signal onto the pad. the output signal can be routed to the buffer directly from the internal logic or through an optional iob output flip-flop. the 3-state control of the output can also be routed directly from the internal logic or through a flip-flip that provides syn- chronous enable and disable. each output driver can be individually programmed for a wide range of low-voltage signalling standards. each output buffer can source up to 24 ma and sink up to 48ma. drive strength and slew rate controls minimize bus transients. in most signalling standards, the output high voltage depends on an externally supplied v cco voltage. the need to supply v cco imposes constraints on which standards can be used in close proximity to each other. see i/o bank- ing , page 3 . an optional weak-keeper circuit is connected to each out- put. when selected, the circuit monitors the voltage on the pad and weakly drives the pin high or low to match the input signal. if the pin is connected to a multiple-source sig- nal, the weak keeper holds the signal in its last state if all drivers are disabled. maintaining a valid logic level in this way eliminates bus chatter. because the weak-keeper circuit uses the iob input buffer to monitor the input level, an appropriate v ref voltage must be provided if the signalling standard requires one. the pro- vision of this voltage must comply with the i/o banking rules. i/o banking some of the i/o standards described above require v cco and/or v ref voltages. these voltages externally and con- nected to device pins that serve groups of iobs, called banks. consequently, restrictions exist about which i/o standards can be combined within a given bank. eight i/o banks result from separating each edge of the fpga into two banks, as shown in figure 3 . each bank has multiple v cco pins, all of which must be connected to the same voltage. this voltage is determined by the output standards in use. within a bank, output standards can be mixed only if they use the same v cco . compatible standards are shown in ta b l e 2 . gtl and gtl+ appear under all voltages because their open-drain outputs do not depend on v cco . some input standards require a user-supplied threshold voltage, v ref . in this case, certain user-i/o pins are auto- matically configured as inputs for the v ref voltage. approx- imately one in six of the i/o pins in the bank assume this role. the v ref pins within a bank are interconnected internally and consequently only one v ref voltage can be used within each bank. all v ref pins in the bank, however, must be con- nected to the external voltage source for correct operation. within a bank, inputs that require v ref can be mixed with those that do not. however, only one v ref voltage can be used within a bank. input buffers that use v ref are not 5 v tolerant. lvttl, lvcmos2, and pci 33 mhz 5 v, are 5 v tolerant. the v cco and v ref pins for each bank appear in the device pinout tables and diagrams. the diagrams also show the bank affiliation of each i/o. within a given package, the number of v ref and v cco pins can vary depending on the size of device. in larger devices, figure 3: virtex i/o banks ta b l e 2 : compatible output standards v cco compatible standards 3.3 v pci, lvttl, sstl3 i, sstl3 ii, ctt, agp, gtl, gtl+ 2.5 v sstl2 i, sstl2 ii, lvcmos2, gtl, gtl+ 1.5 v hstl i, hstl iii, hstl iv, gtl, gtl+ x8778_b bank 0 gclk3 gclk2 gclk1 gclk0 bank 1 bank 5 bank 4 virtex device bank 7 bank 6 bank 2 bank 3
virtex ? 2.5 v field programmable gate arrays r module 2 of 4 www.xilinx.com ds003-2 (v2.5) april 2, 2001 4 1-800-255-7778 product specification more i/o pins convert to v ref pins. since these are always a superset of the v ref pins used for smaller devices, it is possible to design a pcb that permits migration to a larger device if necessary. all the v ref pins for the largest device anticipated must be connected to the v ref voltage, and not used for i/o. in smaller devices, some v cco pins used in larger devices do not connect within the package. these unconnected pins can be left unconnected externally, or can be connected to the v cco voltage to permit migration to a larger device if necessary. in tq144 and pq/hq240 packages, all v cco pins are bonded together internally, and consequently the same v cco voltage must be connected to all of them. in the cs144 package, bank pairs that share a side are intercon- nected internally, permitting four choices for v cco . in both cases, the v ref pins remain internally connected as eight banks, and can be used as described previously. configurable logic block the basic building block of the virtex clb is the logic cell (lc). an lc includes a 4-input function generator, carry logic, and a storage element. the output from the function generator in each lc drives both the clb output and the d input of the flip-flop. each virtex clb contains four lcs, organized in two similar slices, as shown in figure 4 . figure 5 shows a more detailed view of a single slice. in addition to the four basic lcs, the virtex clb contains logic that combines function generators to provide functions of five or six inputs. consequently, when estimating the number of system gates provided by a given device, each clb counts as 4.5 lcs. look-up tables virtex function generators are implemented as 4-input look-up tables (luts). in addition to operating as a function generator, each lut can provide a 16 x 1-bit synchronous ram. furthermore, the two luts within a slice can be com- bined to create a 16 x 2-bit or 32 x 1-bit synchronous ram, or a 16x1-bit dual-port synchronous ram. the virtex lut can also provide a 16-bit shift register that is ideal for capturing high-speed or burst-mode data. this mode can also be used to store data in applications such as digital signal processing. storage elements the storage elements in the virtex slice can be configured either as edge-triggered d-type flip-flops or as level-sensi- tive latches. the d inputs can be driven either by the func- tion generators within the slice or directly from slice inputs, bypassing the function generators. in addition to clock and clock enable signals, each slice has synchronous set and reset signals (sr and by). sr forces a storage element into the initialization state speci- fied for it in the configuration. by forces it into the opposite state. alternatively, these signals can be configured to oper- ate asynchronously. all of the control signals are indepen- dently invertible, and are shared by the two flip-flops within the slice. figure 4: 2-slice virtex clb f1 f2 f3 f4 g1 g2 g3 g4 carry & control carry & control carry & control carry & control lut cin cin cout cout yq xq xq yq x xb y yb yb y bx by bx by g1 g2 g3 g4 f1 f2 f3 f4 slice_b.eps slice 1 slice 0 xb x lut lut lut d ec q rc sp d ec q rc sp d ec q rc sp d ec q rc sp
virtex ? 2.5 v field programmable gate arrays r ds003-2 (v2.5) april 2, 2001 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 5 additional logic the f5 multiplexer in each slice combines the function gen- erator outputs. this combination provides either a function generator that can implement any 5-input function, a 4:1 multiplexer, or selected functions of up to nine inputs. similarly, the f6 multiplexer combines the outputs of all four function generators in the clb by selecting one of the f5-multiplexer outputs. this permits the implementation of any 6-input function, an 8:1 multiplexer, or selected func- tions of up to 19 inputs. each clb has four direct feedthrough paths, one per lc. these paths provide extra data input lines or additional local routing that does not consume logic resources. arithmetic logic dedicated carry logic provides fast arithmetic carry capabil- ity for high-speed arithmetic functions. the virtex clb sup- ports two separate carry chains, one per slice. the height of the carry chains is two bits per clb. the arithmetic logic includes an xor gate that allows a 1-bit full adder to be implemented within an lc. in addition, a dedicated and gate improves the efficiency of multiplier implementation. the dedicated carry path can also be used to cascade func- tion generators for implementing wide logic functions. bufts each virtex clb contains two 3-state drivers (bufts) that can drive on-chip busses. see dedicated routing , page 7 . each virtex buft has an independent 3-state control pin and an independent input pin. block selectram virtex fpgas incorporate several large block selectram memories. these complement the distributed lut selec- trams that provide shallow ram structures implemented in clbs. block selectram memory blocks are organized in columns. all virtex devices contain two such columns, one along each vertical edge. these columns extend the full height of the chip. each memory block is four clbs high, and conse- quently, a virtex device 64 clbs high contains 16 memory blocks per column, and a total of 32 blocks. ta b l e 3 shows the amount of block selectram memory that is available in each virtex device. figure 5: detailed view of virtex slice by f5in sr clk ce bx yb y yq xb x xq g4 g3 g2 g1 f4 f3 f2 f1 cin 0 1 1 0 f5 f5 viewslc4.eps cout cy d ec q d ec q f6 ck wso wsh we a4 by dg bx di di o we i3 i2 i1 i0 lut cy i3 i2 i1 i0 o di we lut init init rev rev ta b l e 3 : virtex block selectram amounts device # of blocks total block selectram bits xcv50 8 32,768 xcv100 10 40,960 xcv150 12 49,152 xcv200 14 57,344 xcv300 16 65,536 xcv400 20 81,920 xcv600 24 98,304 xcv800 28 114,688 xcv1000 32 131,072
virtex ? 2.5 v field programmable gate arrays r module 2 of 4 www.xilinx.com ds003-2 (v2.5) april 2, 2001 6 1-800-255-7778 product specification each block selectram cell, as illustrated in figure 6 , is a fully synchronous dual-ported 4096-bit ram with indepen- dent control signals for each port. the data widths of the two ports can be configured independently, providing built-in bus-width conversion. ta b l e 4 shows the depth and width aspect ratios for the block selectram. the virtex block selectram also includes dedicated rout- ing to provide an efficient interface with both clbs and other block selectrams. programmable routing matrix it is the longest delay path that limits the speed of any worst-case design. consequently, the virtex routing archi- tecture and its place-and-route software were defined in a single optimization process. this joint optimization mini- mizes long-path delays, and consequently, yields the best system performance. the joint optimization also reduces design compilation times because the architecture is software-friendly. design cycles are correspondingly reduced due to shorter design iteration times. local routing the versablock provides local routing resources, as shown in figure 7 , providing the following three types of connec- tions. interconnections among the luts, flip-flops, and grm internal clb feedback paths that provide high-speed connections to luts within the same clb, chaining them together with minimal routing delay direct paths that provide high-speed connections between horizontally adjacent clbs, eliminating the delay of the grm. figure 6: dual-port block selectram web enb rstb clkb addrb[#:0] dib[#:0] wea ena rsta clka addra[#:0] dia[#:0] doa[#:0] dob[#:0] ramb4_s#_s# xcv_ds_006 ta b l e 4 : block selectram port aspect ratios width depth addr bus data bus 1 4096 addr<11:0> data<0> 2 2048 addr<10:0> data<1:0> 4 1024 addr<9:0> data<3:0> 8 512 addr<8:0> data<7:0> 16 256 addr<7:0> data<15:0> figure 7: virtex local routing x8794b clb grm to adjacent grm to adjacent grm direct connection to adjacent clb to adjacent grm to adjacent grm direct connection to adjacent clb
virtex ? 2.5 v field programmable gate arrays r ds003-2 (v2.5) april 2, 2001 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 7 general purpose routing most virtex signals are routed on the general purpose rout- ing, and consequently, the majority of interconnect resources are associated with this level of the routing hier- archy. the general routing resources are located in horizon- tal and vertical routing channels associated with the rows and columns clbs. the general-purpose routing resources are listed below. adjacent to each clb is a general routing matrix (grm). the grm is the switch matrix through which horizontal and vertical routing resources connect, and is also the means by which the clb gains access to the general purpose routing. 24 single-length lines route grm signals to adjacent grms in each of the four directions. 72 buffered hex lines route grm signals to another grms six-blocks away in each one of the four directions. organized in a staggered pattern, hex lines can be driven only at their endpoints. hex-line signals can be accessed either at the endpoints or at the midpoint (three blocks from the source). one third of the hex lines are bidirectional, while the remaining ones are uni-directional. 12 longlines are buffered, bidirectional wires that distribute signals across the device quickly and efficiently. vertical longlines span the full height of the device, and horizontal ones span the full width of the device. i/o routing virtex devices have additional routing resources around their periphery that form an interface between the clb array and the iobs. this additional routing, called the versaring, facilitates pin-swapping and pin-locking, such that logic redesigns can adapt to existing pcb layouts. time-to-mar- ket is reduced, since pcbs and other system components can be manufactured while the logic design is still in progress. dedicated routing some classes of signal require dedicated routing resources to maximize performance. in the virtex architecture, dedi- cated routing resources are provided for two classes of sig- nal. horizontal routing resources are provided for on-chip 3-state busses. four partitionable bus lines are provided per clb row, permitting multiple busses within a row, as shown in figure 8 . two dedicated nets per clb propagate carry signals vertically to the adjacent clb. global routing global routing resources distribute clocks and other sig- nals with very high fanout throughout the device. virtex devices include two tiers of global routing resources referred to as primary global and secondary local clock rout- ing resources. the primary global routing resources are four dedicated global nets with dedicated input pins that are designed to distribute high-fanout clock signals with minimal skew. each global clock net can drive all clb, iob, and block ram clock pins. the primary global nets can only be driven by global buffers. there are four global buffers, one for each global net. the secondary local clock routing resources consist of 24 backbone lines, 12 across the top of the chip and 12 across bottom. from these lines, up to 12 unique signals per column can be distributed via the 12 longlines in the column. these secondary resources are more flexible than the primary resources since they are not restricted to routing only to clock pins. clock distribution virtex provides high-speed, low-skew clock distribution through the primary global routing resources described above. a typical clock distribution net is shown in figure 9 . four global buffers are provided, two at the top center of the device and two at the bottom center. these drive the four primary global nets that in turn drive any clock pin. figure 8: buft connections to dedicated horizontal bus lines clb clb clb clb buft_c.eps tri-state lines
virtex ? 2.5 v field programmable gate arrays r module 2 of 4 www.xilinx.com ds003-2 (v2.5) april 2, 2001 8 1-800-255-7778 product specification four dedicated clock pads are provided, one adjacent to each of the global buffers. the input to the global buffer is selected either from these pads or from signals in the gen- eral purpose routing. delay-locked loop (dll) associated with each global clock input buffer is a fully digi- tal delay-locked loop (dll) that can eliminate skew between the clock input pad and internal clock-input pins throughout the device. each dll can drive two global clock networks.the dll monitors the input clock and the distrib- uted clock, and automatically adjusts a clock delay element. clock edges reach internal flip-flops one to four clock peri- ods after they arrive at the input. this closed-loop system effectively eliminates clock-distribution delay by ensuring that clock edges arrive at internal flip-flops in synchronism with clock edges arriving at the input. in addition to eliminating clock-distribution delay, the dll provides advanced control of multiple clock domains. the dll provides four quadrature phases of the source clock, can double the clock, or divide the clock by 1.5, 2, 2.5, 3, 4, 5, 8, or 16. the dll also operates as a clock mirror. by driving the out- put from a dll off-chip and then back on again, the dll can be used to de-skew a board level clock among multiple vir- tex devices. in order to guarantee that the system clock is operating cor- rectly prior to the fpga starting up after configuration, the dll can delay the completion of the configuration process until after it has achieved lock. see dll timing parameters , page 21 of module 3, for fre- quency range information. boundary scan virtex devices support all the mandatory boundary-scan instructions specified in the ieee standard 1149.1. a test access port (tap) and registers are provided that imple- ment the extest, intest, sample/preload, bypass, idcode, usercode, and highz instructions. the tap also supports two internal scan chains and configura- tion/readback of the device.the tap uses dedicated pack- age pins that always operate using lvttl. for tdo to operate using lvttl, the v cco for bank 2 should be 3.3 v. otherwise, tdo switches rail-to-rail between ground and v cco . boundary-scan operation is independent of individual iob configurations, and unaffected by package type. all iobs, including un-bonded ones, are treated as independent 3-state bidirectional pins in a single scan chain. retention of the bidirectional test capability after configuration facilitates the testing of external interconnections. ta b l e 5 lists the boundary-scan instructions supported in virtex fpgas. internal signals can be captured during extest by connecting them to un-bonded or unused iobs. they can also be connected to the unused outputs of iobs defined as unidirectional input pins. before the device is configured, all instructions except user1 and user2 are available. after configuration, all instructions are available. during configuration, it is recom- mended that those operations using the boundary-scan register (sample/preload, intest, extest) not be performed. figure 9: global clock distribution network global clock spine global clock column gclkpad2 gclkbuf2 gclkpad3 gclkbuf3 gclkbuf1 gclkpad1 gclkbuf0 gclkpad0 global clock rows gclkbu_2.eps
virtex ? 2.5 v field programmable gate arrays r ds003-2 (v2.5) april 2, 2001 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 9 in addition to the test instructions outlined above, the boundary-scan circuitry can be used to configure the fpga, and also to read back the configuration data. figure 10 is a diagram of the virtex series boundary scan logic. it includes three bits of data register per iob, the ieee 1149.1 test access port controller, and the instruction register with decodes. instruction set the virtex series boundary scan instruction set also includes instructions to configure the device and read back configuration data (cfg_in, cfg_out, and jstart). the complete instruction set is coded as shown in ta b l e 5 . data registers the primary data register is the boundary scan register. for each iob pin in the fpga, bonded or not, it includes three bits for in, out, and 3-state control. non-iob pins have appropriate partial bit population if input-only or output-only. each extest captured-or state captures all in, out, and 3-state pins. the other standard data register is the single flip-flop bypass register. it synchronizes data being passed through the fpga to the next downstream boundary scan device. the fpga supports up to two additional internal scan chains that can be specified using the bscan macro. the macro provides two user pins (sel1 and sel2) which are decodes of the user1 and user2 instructions respec- tively. for these instructions, two corresponding pins (tdo1 and tdo2) allow user scan data to be shifted out of tdo. likewise, there are individual clock pins (drck1 and drck2) for each user register. there is a common input pin (tdi) and shared output pins that represent the state of the tap controller (reset, shift, and update). bit sequence the order within each iob is: in, out, 3-state. the input-only pins contribute only the in bit to the boundary scan i/o data register, while the output-only pins contributes all three bits. from a cavity-up view of the chip (as shown in epic), start- ing in the upper right chip corner, the boundary scan data-register bits are ordered as shown in figure 11 . bsdl (boundary scan description language) files for vir- tex series devices are available on the xilinx web site in the file download area. figure 10: virtex series boundary scan logic d q d q iob iob iob iob iob iob iob iob iob iob iob iob iob m u x bypass register iob iob tdo tdi iob iob iob 1 0 1 0 1 0 1 0 1 0 sd le dq d q d q 1 0 1 0 1 0 1 0 dq le sd sd le dq sd le dq iob d q 1 0 dq le sd iob.t data in iob.i iob.q iob.t iob.i shift/ capture clock data register dataout update extest x9016 instruction register
virtex ? 2.5 v field programmable gate arrays r module 2 of 4 www.xilinx.com ds003-2 (v2.5) april 2, 2001 10 1-800-255-7778 product specification identification registers the idcode register is supported. by using the idcode, the device connected to the jtag port can be determined. the idcode register has the following binary format: vvvv:ffff:fffa:aaaa:aaaa:cccc:cccc:ccc1 where v = the die version number f = the family code (03h for virtex family) a = the number of clb rows (ranges from 010h for xcv50 to 040h for xcv1000) c = the company code (49h for xilinx) the usercode register is supported. by using the user- code, a user-programmable identification code can be loaded and shifted out for examination. the identification code is embedded in the bitstream during bitstream gener- ation and is valid only after configuration. including boundary scan in a design since the boundary scan pins are dedicated, no special ele- ment needs to be added to the design unless an internal data register (user1 or user2) is desired. if an internal data register is used, insert the boundary scan symbol and connect the necessary pins as appropriate. development system virtex fpgas are supported by the xilinx foundation and alliance cae tools. the basic methodology for virtex design consists of three interrelated steps: design entry, imple- mentation, and verification. industry-standard tools are used for design entry and simulation (for example, synop- sys fpga express), while xilinx provides proprietary archi- tecture-specific tools for implementation. the xilinx development system is integrated under the xil- inx design manager (xdm ? ) software, providing designers figure 11: boundary scan bit sequence table 5: boundary scan instructions boundary-scan command binary code(4:0) description extest 00000 enables boundary-scan extest operation sample/preload 00001 enables boundary-scan sample/preload operation user 1 00010 access user-defined register 1 user 2 00011 access user-defined register 2 cfg_out 00100 access the configuration bus for read operations. cfg_in 00101 access the configuration bus for write operations. intest 00111 enables boundary-scan intest operation usercode 01000 enables shifting out user code idcode 01001 enables shifting out of id code highz 01010 3-states output pins while enabling the bypass register jstart 01100 clock the start-up sequence when startupclk is tck bypass 11111 enables bypass reserved all other codes xilinx reserved instructions bit 0 ( tdo end) bit 1 bit 2 right half of top-edge iobs (right-to-left) gclk2 gclk3 left half of top-edge iobs (right-to-left) left-edge iobs (top-to-bottom) m1 m0 m2 left half of bottom-edge iobs (left-to-right) gclk1 gclk0 right half of bottom-edge iobs (left-to-right) done prog right-edge iobs (bottom -to-top) cclk (tdi end) 990602001 ta b l e 6 : idcodes assigned to virtex fpgas fpga idcode xcv50 v0610093h xcv100 v0614093h xcv150 v0618093h xcv200 v061c093h xcv300 v0620093h xcv400 v0628093h xcv600 v0630093h xcv800 v0638093h xcv1000 v0640093h
virtex ? 2.5 v field programmable gate arrays r ds003-2 (v2.5) april 2, 2001 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 11 with a common user interface regardless of their choice of entry and verification tools. the xdm software simplifies the selection of implementation options with pull-down menus and on-line help. application programs ranging from schematic capture to placement and routing (par) can be accessed through the xdm software. the program command sequence is gener- ated prior to execution, and stored for documentation. several advanced software features facilitate virtex design. rpms, for example, are schematic-based macros with rela- tive location constraints to guide their placement. they help ensure optimal implementation of common functions. for hdl design entry, the xilinx fpga foundation develop- ment system provides interfaces to the following synthesis design environments. synopsys (fpga compiler, fpga express) exemplar (spectrum) synplicity (synplify) for schematic design entry, the xilinx fpga foundation and alliance development system provides interfaces to the following schematic-capture design environments. mentor graphics v8 (design architect, quicksim ii) viewlogic systems (viewdraw) third-party vendors support many other environments. a standard interface-file specification, electronic design interchange format (edif), simplifies file transfers into and out of the development system. virtex fpgas supported by a unified library of standard functions. this library contains over 400 primitives and mac- ros, ranging from 2-input and gates to 16-bit accumulators, and includes arithmetic functions, comparators, counters, data registers, decoders, encoders, i/o functions, latches, boolean functions, multiplexers, shift registers, and barrel shifters. the ? soft macro ? portion of the library contains detailed descriptions of common logic functions, but does not con- tain any partitioning or placement information. the perfor- mance of these macros depends, therefore, on the partitioning and placement obtained during implementation. rpms, on the other hand, do contain predetermined parti- tioning and placement information that permits optimal implementation of these functions. users can create their own library of soft macros or rpms based on the macros and primitives in the standard library. the design environment supports hierarchical design entry, with high-level schematics that comprise major functional blocks, while lower-level schematics define the logic in these blocks. these hierarchical design elements are auto- matically combined by the implementation tools. different design entry tools can be combined within a hierarchical design, thus allowing the most convenient entry method to be used for each portion of the design. design implementation the place-and-route tools (par) automatically provide the implementation flow described in this section. the parti- tioner takes the edif net list for the design and maps the logic into the architectural resources of the fpga (clbs and iobs, for example). the placer then determines the best locations for these blocks based on their interconnec- tions and the desired performance. finally, the router inter- connects the blocks. the par algorithms support fully automatic implementation of most designs. for demanding applications, however, the user can exercise various degrees of control over the pro- cess. user partitioning, placement, and routing information is optionally specified during the design-entry process. the implementation of highly structured designs can benefit greatly from basic floor planning. the implementation software incorporates timing wizard ? timing-driven placement and routing. designers specify tim- ing requirements along entire paths during design entry. the timing path analysis routines in par then recognize these user-specified requirements and accommodate them. timing requirements are entered on a schematic in a form directly relating to the system requirements, such as the tar- geted clock frequency, or the maximum allowable delay between two registers. in this way, the overall performance of the system along entire signal paths is automatically tai- lored to user-generated specifications. specific timing infor- mation for individual nets is unnecessary. design verification in addition to conventional software simulation, fpga users can use in-circuit debugging techniques. because xilinx devices are infinitely reprogrammable, designs can be veri- fied in real time without the need for extensive sets of soft- ware simulation vectors. the development system supports both software simulation and in-circuit debugging techniques. for simulation, the system extracts the post-layout timing information from the design database, and back-annotates this information into the net list for use by the simulator. alternatively, the user can verify timing-critical portions of the design using the trace ? static timing analyzer. for in-circuit debugging, the development system includes a download and readback cable. this cable connects the fpga in the target system to a pc or workstation. after downloading the design into the fpga, the designer can single-step the logic, readback the contents of the flip-flops, and so observe the internal logic state. simple modifica- tions can be downloaded into the system in a matter of min- utes. configuration virtex devices are configured by loading configuration data into the internal configuration memory. some of the pins
virtex ? 2.5 v field programmable gate arrays r module 2 of 4 www.xilinx.com ds003-2 (v2.5) april 2, 2001 12 1-800-255-7778 product specification used for this are dedicated configuration pins, while others can be re-used as general purpose inputs and outputs once configuration is complete. the dedicated pins are the mode pins (m2, m1, m0), the configuration clock pin (cclk), the init pin, the done pin and the boundary-scan pins (tdi, tdo, tms, tck). depending on the configuration mode chosen, cclk can be an output generated by the fpga, or can be generated externally, and provided to the fpga as an input. note that some configuration pins can act as outputs. for correct operation, these pins can require a v cco of 3.3 v to permit lvttl operation. all the pins affected fall in banks 2 or 3. after virtex devices are configured, unused iobs function as 3-state obufts with weak pull downs. for a more detailed description than that given below, see the xapp138, virtex configuration and readback. configuration modes virtex supports the following four configuration modes. slave-serial mode master-serial mode selectmap mode boundary-scan mode the configuration mode pins (m2, m1, m0) select among these configuration modes with the option in each case of having the iob pins either pulled up or left floating prior to configuration. the selection codes are listed in ta b l e 7 . configuration through the boundary-scan port is always available, independent of the mode selection. selecting the boundary-scan mode simply turns off the other modes. the three mode pins have internal pull-up resistors, and default to a logic high if left unconnected. slave serial mode in slave serial mode, the fpga receives configuration data in bit-serial form from a serial prom or other source of serial configuration data. the serial bitstream must be setup at the din input pin a short time before each rising edge of an externally generated cclk. for more information on serial proms, see the prom data sheet at http://www.xilinx.com/partinfo/ds026.pdf . multiple fpgas can be daisy-chained for configuration from a single source. after a particular fpga has been config- ured, the data for the next device is routed to the dout pin. the data on the dout pin changes on the rising edge of cclk. the change of dout on the rising edge of cclk differs from previous families, but will not cause a problem for mixed configuration chains. this change was made to improve serial-configuration rates for virtex only chains. figure 12 shows a full master/slave system. a virtex device in slave serial mode should be connected as shown in the third device from the left slave-serial mode is selected by applying <111> or <011> to the mode pins (m2, m1, m0). a weak pull-up on the mode pins makes slave serial the default mode if the pins are left unconnected. figure 13 shows slave-serial configuration timing. ta b l e 8 provides more detail about the characteristics shown in figure 13 . configuration must be delayed until the init pins of all daisy-chained fpgas are high. table 7: configuration codes configuration mode m2 m1 m0 cclk direction data width serial d out configuration pull-ups master-serial mode 0 0 0 out 1 yes no boundary-scan mode 1 0 1 n/a 1 no no selectmap mode 1 1 0 in 8 no no slave-serial mode 1 1 1 in 1 yes no master-serial mode 1 0 0 out 1 yes yes boundary-scan mode 0 0 1 n/a 1 no yes selectmap mode 0 1 0 in 8 no yes slave-serial mode 0 1 1 in 1 yes yes
virtex ? 2.5 v field programmable gate arrays r ds003-2 (v2.5) april 2, 2001 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 13 table 8: master/slave serial mode programming switching description symbol units cclk din setup/hold, slave mode 1/2 t dcc /t ccd 5.0 / 0 ns, min din setup/hold, master mode 1/2 t dsck /t sckd 5.0 / 0 ns, min dout 3 t cco 12.0 ns, max high time 4 t cch 5.0 ns, min low time 5 t ccl 5.0 ns, min maximum frequency f cc 66 mhz, max frequency tolerance, master mode with respect to nominal +45% ? 30% figure 12: master/slave serial mode circuit diagram virtex master serial virtex, xc4000xl, slave xc1701l program m2 m0 m1 dout cclk clk data ce ceo reset/oe done din init init done program program cclk din dout m2 m0 m1 (low reset option used) 4.7 k xcv_12_091499 3.3v v cc optional pull-up resistor on done note 1: if none of the virtex fpgas have been selected to drive done, an external pull-up resistor of 330 ? should be added to the common done line. 1 figure 13: slave serial mode programming switching characteristics 4 t cch 3 t cco 5 t ccl 2 t ccd 1 t dcc din cclk dout (output) x5379_a
virtex ? 2.5 v field programmable gate arrays r module 2 of 4 www.xilinx.com ds003-2 (v2.5) april 2, 2001 14 1-800-255-7778 product specification master serial mode in master serial mode, the cclk output of the fpga drives a xilinx serial prom that feeds bit-serial data to the din input. the fpga accepts this data on each rising cclk edge. after the fpga has been loaded, the data for the next device in a daisy-chain is presented on the dout pin after the rising cclk edge. the interface is identical to slave serial except that an inter- nal oscillator is used to generate the configuration clock (cclk). a wide range of frequencies can be selected for cclk which always starts at a slow default frequency. con- figuration bits then switch cclk to a higher frequency for the remainder of the configuration. switching to a lower fre- quency is prohibited. the cclk frequency is set using the configrate option in the bitstream generation software. the maximum cclk fre- quency that can be selected is 60 mhz. when selecting a cclk frequency, ensure that the serial prom and any daisy-chained fpgas are fast enough to support the clock rate. on power-up, the cclk frequency is 2.5 mhz. this fre- quency is used until the configrate bits have been loaded when the frequency changes to the selected configrate. unless a different frequency is specified in the design, the default configrate is 4 mhz. figure 12 shows a full master/slave system. in this system, the left-most device operates in master-serial mode. the remaining devices operate in slave-serial mode. the sprom reset pin is driven by init , and the ce input is driven by done. there is the potential for contention on the done pin, depending on the start-up sequence options chosen. figure 13 shows the timing of master-serial configuration. master serial mode is selected by a <000> or <100> on the mode pins (m2, m1, m0). ta b l e 8 shows the timing informa- tion for figure 13 . at power-up, v cc must rise from 1.0 v to v cc min in less than 50 ms, otherwise delay configuration by pulling pro- gram low until v cc is valid. the sequence of operations necessary to configure a virtex fpga serially appears in figure 14 . selectmap mode the selectmap mode is the fastest configuration option. byte-wide data is written into the fpga with a busy flag controlling the flow of data. an external data source provides a byte stream, cclk, a chip select (cs ) signal and a write signal (write ). if busy is asserted (high) by the fpga, the data must be held until busy goes low. data can also be read using the selectmap mode. if write is not asserted, configuration data is read out of the fpga as part of a readback operation. in the selectmap mode, multiple virtex devices can be chained in parallel. data pins (d7:d0), cclk, write , busy , prog, done, and init can be connected in parallel between all the fpgas. note that the data is organized with the msb of each byte on pin do and the lsb of each byte on d7. the cs pins are kept separate, insuring that each fpga can be selected individually. write should be low before loading the first bitstream and returned high after the last device has been programmed. use cs to select the appropriate fpga for loading the bitstream and sending the configuration data. at the end of the bitstream, deselect the loaded device and select the next target fpga by setting its cs pin high. a free-running oscillator or other externally generated signal can be used for cclk. the busy signal can be ignored for frequencies below 50 mhz. for details about frequencies above 50 mhz, see xapp138, virtex configuration and readback. once all the devices have been programmed, the done pin goes high.
virtex ? 2.5 v field programmable gate arrays r ds003-2 (v2.5) april 2, 2001 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 15 after configuration, the pins of the selectmap port can be used as additional user i/o. alternatively, the port can be retained to permit high-speed 8-bit readback. retention of the selectmap port is selectable on a design-by-design basis when the bitstream is generated. if retention is selected, prohibit constraints are required to prevent the selectmap-port pins from being used as user i/o. multiple virtex fpgas can be configured using the select- map mode, and be made to start-up simultaneously. to configure multiple devices in this way, wire the individual cclk, data, write , and busy pins of all the devices in parallel. the individual devices are loaded separately by asserting the cs pin of each device in turn and writing the appropriate data. s ee ta bl e 9 for selectmap write timing characteristics. . write write operations send packets of configuration data into the fpga. the sequence of operations for a multi-cycle write operation is shown below. note that a configuration packet can be split into many such sequences. the packet does not have to complete within one assertion of cs , illustrated in figure 15 . 1. assert write and cs low. note that when cs is asserted on successive cclks, write must remain either asserted or de-asserted. otherwise an abort will be initiated, as described below. 2. drive data onto d[7:0]. note that to avoid contention, the data source should not be enabled while cs is low and write is high. similarly, while write is high, no more that one cs should be asserted. figure 14: serial configuration flowchart apply power set program = high release init if used to delay configuration load a configuration bit high low fpga makes a final clearing pass and releases init when finished. fpga starts to clear configuration memory. ds003_154_111799 configuration completed end of bitstream? yes no once per bitstream, fpga checks data using crc and pulls init low on error. if no crc errors found, fpga enters start-up phase causing done to go high. init? table 9: selectmap write timing characteristics description symbol units cclk d 0-7 setup/hold 1/2 t smdcc /t smccd 5.0 / 1.7 ns, min cs setup/hold 3/4 t smcscc /t smcccs 7.0 / 1.7 ns, min write setup/hold 5/6 t smccw /t smwcc 7.0 / 1.7 ns, min busy propagation delay 7 t smckby 12.0 ns, max maximum frequency f cc 66 mhz, max maximum frequency with no handshake f ccnh 50 mhz, max
virtex ? 2.5 v field programmable gate arrays r module 2 of 4 www.xilinx.com ds003-2 (v2.5) april 2, 2001 16 1-800-255-7778 product specification 3. at the rising edge of cclk: if busy is low, the data is accepted on this clock. if busy is high (from a previous write), the data is not accepted. acceptance will instead occur on the first clock after busy goes low, and the data must be held until this has happened. 4. repeat steps 2 and 3 until all the data has been sent. 5. de-assert cs and write . a flowchart for the write operation appears in figure 16 . note that if cclk is slower than f ccnh , the fpga will never assert busy, in this case, the above handshake is unnec- essary, and data can simply be entered into the fpga every cclk cycle. figure 15: write operations ds003_16_102199 cclk write write no write write data[7:0] cs write 3 5 busy 4 6 7 1 2
virtex ? 2.5 v field programmable gate arrays r ds003-2 (v2.5) april 2, 2001 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 17 abort during a given assertion of cs , the user cannot switch from a write to a read, or vice-versa. this action causes the cur- rent packet command to be aborted. the device will remain busy until the aborted operation has completed. following an abort, data is assumed to be unaligned to word bound- aries, and the fpga requires a new synchronization word prior to accepting any new packets. to initiate an abort during a write operation, de-assert write . at the rising edge of cclk, an abort is initiated, as shown in figure 17 . figure 16: selectmap flowchart for write operation apply power set program = high release init if used to delay configuration on first fpga set write = low enter data source set cs = low on first fpga set cs = high apply configuration byte init? high low busy? low high disable data source set write = high when all done pins are released, done goes high and start-up sequences complete. if no errors, later fpgas enter start-up phase releasing done. if no errors, first fpgas enter start-up phase releasing done. once per bitstream, fpga checks data using crc and pulls init low on error. fpga makes a final clearing pass and releases init when finished. fpga starts to clear configuration memory. for any other fpgas ds003_17_111799 repeat sequence a configuration completed sequence a end of data? yes no
virtex ? 2.5 v field programmable gate arrays r module 2 of 4 www.xilinx.com ds003-2 (v2.5) april 2, 2001 18 1-800-255-7778 product specification boundary-scan mode in the boundary-scan mode, no non-dedicated pins are required, configuration being done entirely through the ieee 1149.1 test access port. configuration through the tap uses the cfg_in instruc- tion. this instruction allows data input on tdi to be con- verted into data packets for the internal configuration bus. the following steps are required to configure the fpga through the boundary-scan port (when using tck as a start-up clock). 1. load the cfg_in instruction into the boundary-scan instruction register (ir) 2. enter the shift-dr (sdr) state 3. shift a configuration bitstream into tdi 4. return to run-test-idle (rti) 5. load the jstart instruction into ir 6. enter the sdr state 7. clock tck through the startup sequence 8. return to rti configuration and readback via the tap is always available. the boundary-scan mode is selected by a <101> or 001> on the mode pins (m2, m1, m0). configuration sequence the configuration of virtex devices is a three-phase pro- cess. first, the configuration memory is cleared. next, con- figuration data is loaded into the memory, and finally, the logic is activated by a start-up process. configuration is automatically initiated on power-up unless it is delayed by the user, as described below. the configura- tion process can also be initiated by asserting program . the end of the memory-clearing phase is signalled by init going high, and the completion of the entire process is sig- nalled by done going high. the power-up timing of configuration signals is shown in figure 18 . the corresponding timing characteristics are listed in ta bl e 1 0 . . delaying configuration init can be held low using an open-drain driver. an open-drain is required since init is a bidirectional open-drain pin that is held low by the fpga while the con- figuration memory is being cleared. extending the time that the pin is low causes the configuration sequencer to wait. thus, configuration is delayed by preventing entry into the phase where data is loaded. start-up sequence the default start-up sequence is that one cclk cycle after done goes high, the global 3-state signal (gts) is released. this permits device outputs to turn on as necessary. one cclk cycle later, the global set/reset (gsr) and glo- bal write enable (gwe) signals are released. this permits the internal storage elements to begin changing state in response to the logic and the user clock. the relative timing of these events can be changed. in addi- tion, the gts, gsr, and gwe events can be made depen- dent on the done pins of multiple devices all going high, forcing the devices to start in synchronism. the sequence can also be paused at any stage until lock has been achieved on any or all dlls. figure 17: selectmap write abort waveforms x8797_c cclk cs write abort data[7:0] busy figure 18: power-up timing configuration signals table 10: power-up timing characteristics description symbol value units power-on reset t por 2.0 ms, max program latency t pl 100.0 m s, max cclk (output) delay t icck 0.5 m s, min 4.0 m s, max program pulse width t program 300 ns, min valid program vcc cclk output or input t pi t icck 98122302 t por init m0, m1, m2 (required)
virtex ? 2.5 v field programmable gate arrays r ds003-2 (v2.5) april 2, 2001 www.xilinx.com module 2 of 4 product specification 1-800-255-7778 19 data stream format virtex devices are configured by sequentially loading frames of data. ta b l e 1 1 lists the total number of bits required to configure each device. for more detailed infor- mation, see application note xapp151 ? virtex configura- tion architecture advanced users guide ? . readback the configuration data stored in the virtex configuration memory can be readback for verification. along with the configuration data it is possible to readback the contents all flip-flops/latches, lutrams, and block rams. this capabil- ity is used for real-time debugging. for more detailed information, see application note xapp138 , virtex fpga series configuration and read- back . table 11: virtex bit-stream lengths device # of configuration bits xcv50 559,200 xcv100 781,216 xcv150 1,040,096 xcv200 1,335,840 xcv300 1,751,808 xcv400 2,546,048 xcv600 3,607,968 xcv800 4,715,616 xcv1000 6,127,744
virtex ? 2.5 v field programmable gate arrays r module 2 of 4 www.xilinx.com ds003-2 (v2.5) april 2, 2001 20 1-800-255-7778 product specification revision history virtex data sheet the virtex data sheet contains the following modules: ds003-1, virtex 2.5v fpgas: introduction and ordering information (module 1) ds003-2, virtex 2.5v fpgas: functional description (module 2) ds003-3, virtex 2.5v fpgas: dc and switching characteristics (module 3) ds003-4, virtex 2.5v fpgas: pinout tables (module 4) date version revision 11/98 1.0 initial xilinx release. 01/99 1.2 updated package drawings and specs. 02/99 1.3 update of package drawings, updated specifications. 05/99 1.4 addition of package drawings and specifications. 05/99 1.5 replaced fg 676 & fg680 package drawings. 07/99 1.6 changed boundary scan information and changed figure 11, boundary scan bit sequence. updated iob input & output delays. added capacitance info for different i/o standards. added 5 v tolerant information. added dll parameters and waveforms and new pin-to-pin input and output parameter tables for global clock input to output and setup and hold. changed configuration information including figures 12, 14, 17 & 19. added device-dependent listings for quiescent currents iccintq and iccoq. updated iob input and output delays based on default standard of lvttl, 12 ma, fast slew rate. added iob input switching characteristics standard adjustments. 09/99 1.7 speed grade update to preliminary status, power-on specification and clock-to-out minimums additions, ? 0 ? hold time listing explanation, quiescent current listing update, and figure 6 addra input label correction. added t ijitcc parameter, changed t ojit to t ophase . 01/00 1.8 update to speed.txt file 1.96. corrections for crs 111036,111137, 112697, 115479, 117153, 117154, and 117612. modified notes for recommended operating conditions (voltage and temperature). changed bank information for v cco in cs144 package on p.43. 01/00 1.9 updated dll jitter parameter table and waveforms, added delay measurement methodology table for different i/o standards, changed buffered hex line info and input/output timing measurement notes. 03/00 2.0 new tbcko values; corrected fg680 package connection drawing; new note about status of cclk pin after configuration. 05/00 2.1 modified ? pins not listed ... ? statement. speed grade update to final status. 05/00 2.2 modified table 18. 09/00 2.3 added xcv400 values to table under minimum clock-to-out for virtex devices . corrected units column in table under iob input switching characteristics . added values to table under clb selectram switching characteristics . 10/00 2.4 corrected pinout information for devices in the bg256, bg432, and bg560 packages in ta bl e 1 8 . corrected bg256 pin function diagram . 04/01 2.5 revised minimums for global clock set-up and hold for lvttl standard, with dll . updated selectmap write timing characteristics values in ta b l e 9 . converted file to modularized format. see the virtex data sheet section.
? 2001 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as listed a t http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. ds003-3 (v2.5) april 2, 2001 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 1 virtex electrical characteristics definition of terms data sheets can be designated as advance or preliminary. the status of specifications in these data sheets is as follows: advance: initial estimates based on simulation and/or extrapolation from other speed grades, devices, or families. values are subject to change. use as estimates, not for production. preliminary: based on preliminary characterization. further changes are not expected. unmarked: data sheets not identified as either advance or preliminary are to be considered final. all specifications are representative of worst-case supply voltage and junction temperature conditions. the parameters included are common to popular designs and typical applications. contact the factory for design considerations requiring more detailed information. all specifications are subject to change without notice. virtex dc characteristics absolute maximum ratings (1) 0 virtex? 2.5 v field programmable gate arrays ds003-3 (v2.5) april 2, 2001 03 product specification symbol description units v ccint supply voltage relative to gnd (2) ?0.5 to 3.0 v v cco supply voltage relative to gnd (2) ?0.5 to 4.0 v v ref input reference voltage ?0.5 to 3.6 v v in input voltage relative to gnd (3) using v ref ?0.5 to 3.6 v internal threshold ?0.5 to 5.5 v v ts voltage applied to 3-state output ?0.5 to 5.5 v v cc longest supply voltage rise time from 1v-2.375v 50 ms t stg storage temperature (ambient) ?65 to +150 c t sol maximum soldering temp. (10s @ 1/16 in. = 1.5 mm) +260 c t j junction temperature plastic packages +125 c notes: 1. stresses beyond those listed under absolute maximum ratings can cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under operating condi tions is not implied. exposure to absolute maximum ratings conditions for extended periods of time can affect device reliability. 2. power supplies can turn on in any order. 3. for protracted periods (e.g., longer than a day), v in should not exceed v cco by more than 3.6 v. r
virtex ? 2.5 v field programmable gate arrays r module 3 of 4 www.xilinx.com ds003-3 (v2.5) april 2, 2001 2 1-800-255-7778 product specification recommended operating conditions symbol description min max units v ccint (1) input supply voltage relative to gnd, t j = 0 c to +85 ccommercial 2.5 ? 5% 2.5 + 5% v input supply voltage relative to gnd, t j = ? 40 c to +100 c industrial 2.5 ? 5% 2.5 + 5% v v cco (4) supply voltage relative to gnd, t j = 0 c to +85 ccommercial1.43.6v supply voltage relative to gnd, t j = ? 40 c to +100 c industrial 1.4 3.6 v t in input signal transition time 250 ns notes: 1. correct operation is guaranteed with a minimum v ccint of 2.375 v (nominal v ccint ? 5%). below the minimum value, all delay parameters increase by 3% for each 50-mv reduction in v ccint below the specified range. 2. at junction temperatures above those listed as operating conditions, delay parameters do increase. please refer to the trce r eport. 3. input and output measurement threshold is ~50% of v cc . 4. min and max values for v cco are i/o standard dependant.
virtex ? 2.5 v field programmable gate arrays r ds003-3 (v2.5) april 2, 2001 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 3 dc characteristics over recommended operating conditions symbol description device min max units v drint data retention v ccint voltage (below which configuration data can be lost) all 2.0 v v drio data retention v cco voltage (below which configuration data can be lost) all 1.2 v i ccintq quiescent v ccint supply current (1,3) xcv50 50 ma xcv100 50 ma xcv150 50 ma xcv200 75 ma xcv300 75 ma xcv400 75 ma xcv600 100 ma xcv800 100 ma xcv1000 100 ma i ccoq quiescent v cco supply current (1) xcv50 2 ma xcv100 2 ma xcv150 2 ma xcv200 2 ma xcv300 2 ma xcv400 2 ma xcv600 2 ma xcv800 2 ma xcv1000 2 ma i ref v ref current per v ref pin all 20 m a i l input or output leakage current all ? 10 +10 m a c in input capacitance (sample tested) bga, pq, hq, packages all 8 pf i rpu pad pull-up (when selected) @ v in = 0 v, v cco = 3.3 v (sample tested) all note (2) 0.25 ma i rpd pad pull-down (when selected) @ v in = 3.6 v (sample tested) note (2) 0.15 ma notes: 1. with no output current loads, no active input pull-up resistors, all i/o pins 3-stated and floating. 2. internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. these pull-up and pull-down resistors do not guarantee valid logic levels when input pins are connected to other circuits. 3. multiply i ccintq limit by two for industrial grade.
virtex ? 2.5 v field programmable gate arrays r module 3 of 4 www.xilinx.com ds003-3 (v2.5) april 2, 2001 4 1-800-255-7778 product specification power-on power supply requirements xilinx fpgas require a certain amount of supply current during power-on to insure proper device operation. the actual current consumed depends on the power-on ramp rate of the power supply. this is the time required to reach the nominal power supply voltage of the device (1) from 0 v. the current is highest at the fastest suggested ramp rate (0 v to nominal voltage in 2 ms) and is lowest at the slowest allowed ramp rate (0 v to nominal voltage in 50 ms). dc input and output levels values for v il and v ih are recommended input voltages. values for i ol and i oh are guaranteed output currents over the recommended operating conditions at the v ol and v oh test points. only selected standards are tested. these are chosen to ensure that all standards meet their specifications. the selected standards are tested at minimum v cco for each standard with the respective v ol and v oh voltage levels shown. other standards are sample tested. product description (2) current requirement (1,3) virtex family, commercial grade minimum required current supply 500 ma virtex family, industrial grade minimum required current supply 2 a notes: 1. ramp rate used for this specification is from 0 - 2.7 vdc. peak current occurs on or near the internal power-on reset thresho ld and lasts for less than 3 ms. 2. devices are guaranteed to initialize properly with the minimum current available from the power supply as noted above. 3. larger currents can result if ramp rates are forced to be faster. input/output standard v il v ih v ol v oh i ol i oh v, min v, max v, min v, max v, max v, min ma ma lvttl (1) ? 0.5 0.8 2.0 5.5 0.4 2.4 24 ? 24 lvcm os 2 ? 0.5 .7 1.7 5.5 0.4 1.9 12 ? 12 pci, 3.3 v ? 0.5 44% v ccint 60% v ccint v cco + 0.5 10% v cco 90% v cco note (2) note (2) pci, 5.0 v ? 0.5 0.8 2.0 5.5 0.55 2.4 note (2) note (2) gtl ? 0.5 v ref ? 0.05 v ref + 0.05 3.6 0.4 n/a 40 n/a gtl+ ? 0.5 v ref ? 0.1 v ref + 0.1 3.6 0.6 n/a 36 n/a hstl i ? 0.5 v ref ? 0.1 v ref + 0.1 3.6 0.4 v cco ? 0.4 8 ? 8 hstl iii ? 0.5 v ref ? 0.1 v ref + 0.1 3.6 0.4 v cco ? 0.4 24 ? 8 hstl iv ? 0.5 v ref ? 0.1 v ref + 0.1 3.6 0.4 v cco ? 0.4 48 ? 8 sstl3 i ? 0.5 v ref ? 0.2 v ref + 0.2 3.6 v ref ? 0.6 v ref + 0.6 8 ? 8 sstl3 ii ? 0.5 v ref ? 0.2 v ref + 0.2 3.6 v ref ? 0.8 v ref + 0.8 16 ? 16 sstl2 i ? 0.5 v ref ? 0.2 v ref + 0.2 3.6 v ref ? 0.61 v ref + 0.61 7.6 ? 7.6 sstl2 ii ? 0.5 v ref ? 0.2 v ref + 0.2 3.6 v ref ? 0.80 v ref + 0.80 15.2 ? 15.2 ctt ? 0.5 v ref ? 0.2 v ref + 0.2 3.6 v ref ? 0.4 v ref + 0.4 8 ? 8 agp ? 0.5 v ref ? 0.2 v ref + 0.2 3.6 10% v cco 90% v cco note (2) note (2) notes: 1. v ol and v oh for lower drive currents are sample tested. 2. tested according to the relevant specifications.
virtex ? 2.5 v field programmable gate arrays r ds003-3 (v2.5) april 2, 2001 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 5 virtex switching characteristics testing of switching parameters is modeled after testing methods specified by mil-m-38510/605. all devices are 100% functionally tested. internal timing parameters are derived from measuring internal test patterns. listed below are representative values. for more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (trce in the xilinx develop- ment system) and back-annotated to the simulation net list. all timing parameters assume worst-case operating condi- tions (supply voltage and junction temperature). values apply to all virtex devices unless otherwise noted. iob input switching characteristics input delays associated with the pad are specified for lvttl levels. for other standards, adjust the delays with the values shown in iob input switching characteristics standard adjustments , page 7 . description device symbol speed grade units min -6 -5 -4 propagation delays pad to i output, no delay all t iopi 0.39 0.8 0.9 1.0 ns, max pad to i output, with delay xcv50 t iopid 0.8 1.5 1.7 1.9 ns, max xcv100 0.8 1.5 1.7 1.9 ns, max xcv150 0.8 1.5 1.7 1.9 ns, max xcv200 0.8 1.5 1.7 1.9 ns, max xcv300 0.8 1.5 1.7 1.9 ns, max xcv400 0.9 1.8 2.0 2.3 ns, max xcv600 0.9 1.8 2.0 2.3 ns, max xcv800 1.1 2.1 2.4 2.7 ns, max xcv1000 1.1 2.1 2.4 2.7 ns, max pad to output iq via transparent latch, no delay all t iopli 0.8 1.6 1.8 2.0 ns, max pad to output iq via transparent latch, with delay xcv50 t ioplid 1.9 3.7 4.2 4.8 ns, max xcv100 1.9 3.7 4.2 4.8 ns, max xcv150 2.0 3.9 4.3 4.9 ns, max xcv200 2.0 4.0 4.4 5.1 ns, max xcv300 2.0 4.0 4.4 5.1 ns, max xcv400 2.1 4.1 4.6 5.3 ns, max xcv600 2.1 4.2 4.7 5.4 ns, max xcv800 2.2 4.4 4.9 5.6 ns, max xcv1000 2.3 4.5 5.1 5.8 ns, max sequential delays clock clk to output iq all t iockiq 0.2 0.7 0.7 0.8 ns, max setup and hold times with respect to clock clk at iob input register (1) setup time / hold time pad, no delay all t iopick /t ioickp 0.8 / 0 1.6 / 0 1.8 / 0 2.0 / 0 ns, min
virtex ? 2.5 v field programmable gate arrays r module 3 of 4 www.xilinx.com ds003-3 (v2.5) april 2, 2001 6 1-800-255-7778 product specification pad, with delay xcv50 t iopickd /t ioickpd 1.9 / 0 3.7 / 0 4.1 / 0 4.7 / 0 ns, min xcv100 1.9 / 0 3.7 / 0 4.1 / 0 4.7 / 0 ns, min xcv150 1.9 / 0 3.8 / 0 4.3 / 0 4.9 / 0 ns, min xcv200 2.0 / 0 3.9 / 0 4.4 / 0 5.0 / 0 ns, min xcv300 2.0 / 0 3.9 / 0 4.4 / 0 5.0 / 0 ns, min xcv400 2.1 / 0 4.1 / 0 4.6 / 0 5.3 / 0 ns, min xcv600 2.1 / 0 4.2 / 0 4.7 / 0 5.4 / 0 ns, min xcv800 2.2 / 0 4.4 / 0 4.9 / 0 5.6 / 0 ns, min xcv1000 2.3 / 0 4.5 / 0 5.0 / 0 5.8 / 0 ns, min ice input all t ioiceck /t iockice 0.37/ 0 0.8 / 0 0.9 / 0 1.0 / 0 ns, max set/reset delays sr input (iff, synchronous) all t iosrcki 0.49 1.0 1.1 1.3 ns, max sr input to iq (asynchronous) all t iosriq 0.70 1.4 1.6 1.8 ns, max gsr to output iq all t gsrq 4.9 9.7 10.9 12.5 ns, max notes: 1. a zero "0" hold time listing indicates no hold time or a negative hold time. negative values cannot be guaranteed "best-case" , but if a "0" is listed, there is no positive hold time. 2. input timing for lvttl is measured at 1.4 v. for other i/o standards, see table 2 . description device symbol speed grade units min -6 -5 -4
virtex ? 2.5 v field programmable gate arrays r ds003-3 (v2.5) april 2, 2001 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 7 iob input switching characteristics standard adjustments iob output switching characteristics output delays terminating at a pad are specified for lvttl with 12 ma drive and fast slew rate. for other standards, adjust the delays with the values shown in iob output switching characteristics standard adjustments , page 9 . description symbol standard (1) speed grade units min-6-5-4 data input delay adjustments standard-specific data input delay adjustments t ilvttl lv t t l 0 0 0 0 n s t ilvcmos2 lv c m o s 2 ? 0.02 ? 0.04 ? 0.04 ? 0.05 ns t ipci33_3 pci, 33 mhz, 3.3 v ? 0.05 ? 0.11 ? 0.12 ? 0.14 ns t ipci33_5 pci, 33 mhz, 5.0 v 0.13 0.25 0.28 0.33 ns t ipci66_3 pci, 66 mhz, 3.3 v ? 0.05 ? 0.11 ? 0.12 ? 0.14 ns t igtl gtl 0.100.200.230.26 ns t igtlp gtl+ 0.06 0.11 0.12 0.14 ns t ihstl hstl 0.02 0.03 0.03 0.04 ns t isstl2 sstl2 ? 0.04 ? 0.08 ? 0.09 ? 0.10 ns t isstl3 sstl3 ? 0.02 ? 0.04 ? 0.05 ? 0.06 ns t ictt ctt 0.010.020.020.02 ns t iagp agp ? 0.03 ? 0.06 ? 0.07 ? 0.08 ns notes: 1. input timing for lvttl is measured at 1.4 v. for other i/o standards, see ta bl e 2 . description symbol speed grade units min-6-5-4 propagation delays o input to pad t ioop 1.2 2.9 3.2 3.5 ns, max o input to pad via transparent latch t ioolp 1.4 3.4 3.7 4.0 ns, max 3-state delays t input to pad high-impedance (1) t iothz 1.0 2.0 2.2 2.4 ns, max t input to valid data on pad t ioton 1.4 3.1 3.3 3.7 ns, max t input to pad high-impedance via transparent latch (1) t iotlphz 1.2 2.4 2.6 3.0 ns, max t input to valid data on pad via transparent latch t iotlpon 1.6 3.5 3.8 4.2 ns, max gts to pad high impedance (1) t gts 2.5 4.9 5.5 6.3 ns, max sequential delays clock clk to pad t iockp 1.0 2.9 3.2 3.5 ns, max clock clk to pad high-impedance (synchronous) (1) t iockhz 1.1 2.3 2.5 2.9 ns, max
virtex ? 2.5 v field programmable gate arrays r module 3 of 4 www.xilinx.com ds003-3 (v2.5) april 2, 2001 8 1-800-255-7778 product specification clock clk to valid data on pad (synchronous) t iockon 1.5 3.4 3.7 4.1 ns, max setup and hold times before/after clock clk (2) setup time / hold time o input t ioock /t iocko 0.51 / 0 1.1 / 0 1.2 / 0 1.3 / 0 ns, min oce input t iooceck /t iockoce 0.37 / 0 0.8 / 0 0.9 / 0 1.0 / 0 ns, min sr input (off) t iosrcko /t iockosr 0.52 / 0 1.1 / 0 1.2 / 0 1.4 / 0 ns, min 3-state setup times, t input t iotck /t iockt 0.34 / 0 0.7 / 0 0.8 / 0 0.9 / 0 ns, min 3-state setup times, tce input t iotceck /t iocktce 0.41 / 0 0.9 / 0 0.9 / 0 1.1 / 0 ns, min 3-state setup times, sr input (tff) t iosrckt /t iocktsr 0.49 / 0 1.0 / 0 1.1 / 0 1.3 / 0 ns, min set/reset delays sr input to pad (asynchronous) t iosrp 1.6 3.8 4.1 4.6 ns, max sr input to pad high-impedance (asynchronous) (1) t iosrhz 1.6 3.1 3.4 3.9 ns, max sr input to valid data on pad (asynchronous) t iosron 2.0 4.2 4.6 5.1 ns, max gsr to pad t iogsrq 4.9 9.7 10.9 12.5 ns, max notes: 1. 3-state turn-off delays should not be adjusted. 2. a zero "0" hold time listing indicates no hold time or a negative hold time. negative values can not be guaranteed "best-case ", but if a "0" is listed, there is no positive hold time. description symbol speed grade units min-6-5-4
virtex ? 2.5 v field programmable gate arrays r ds003-3 (v2.5) april 2, 2001 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 9 iob output switching characteristics standard adjustments output delays terminating at a pad are specified for lvttl with 12 ma drive and fast slew rate. for other standards, adjust the delays by the values shown. description symbol standard (1) speed grade unit s min-6-5-4 output delay adjustments standard-specific adjustments for output delays terminating at pads (based on standard capacitive load, csl) t olvttl_s2 lvttl, slow, 2 ma 4.2 14.7 15.8 17.0 ns t olvttl_s4 4 ma 2.5 7.5 8.0 8.6 ns t olvttl_s6 6 ma 1.8 4.8 5.1 5.6 ns t olvttl_s8 8 ma 1.2 3.0 3.3 3.5 ns t olvttl_s12 12 ma 1.0 1.9 2.1 2.2 ns t olvttl_s16 16 ma 0.9 1.7 1.9 2.0 ns t olvttl_s24 24 ma 0.8 1.3 1.4 1.6 ns t olvttl_f2 lvttl, fast, 2ma 1.9 13.1 14.0 15.1 ns t olvttl_f4 4 ma 0.7 5.3 5.7 6.1 ns t olvttl_f6 6 ma 0.2 3.1 3.3 3.6 ns t olvttl_f8 8 ma 0.1 1.0 1.1 1.2 ns t olvttl_f12 12 ma 0 0 0 0 ns t olvttl_f16 16 ma ? 0.10 ? 0.05 ? 0.05 ? 0.05 ns t olvttl_f24 24 ma ? 0.10 ? 0.20 ? 0.21 ? 0.23 ns t olvcmos2 lvcmos2 0.10 0.10 0.11 0.12 ns t opci33_3 pci, 33 mhz, 3.3 v 0.50 2.3 2.5 2.7 ns t opci33_5 pci, 33 mhz, 5.0 v 0.40 2.8 3.0 3.3 ns t opci66_3 pci, 66 mhz, 3.3 v 0.10 ? 0.40 ? 0.42 ? 0.46 ns t ogtl gtl 0.6 0.50 0.54 0.6 ns t ogtlp gtl+ 0.7 0.8 0.9 1.0 ns t ohstl_i hstl i 0.10 ? 0.50 ? 0.53 ? 0.5 ns t ohstl_iii hstl iii ? 0.10 ? 0.9 ? 0.9 ? 1.0 ns t ohstl_iv hstl iv ? 0.20 ? 1.0 ? 1.0 ? 1.1 ns t osstl2_i sstl2 i ? 0.10 ? 0.50 ? 0.53 ? 0.5 ns t osslt2_ii sstl2 ii ? 0.20 ? 0.9 ? 0.9 ? 1.0 ns t osstl3_i sstl3 i ? 0.20 ? 0.50 ? 0.53 ? 0.5 ns t osstl3_ii sstl3 ii ? 0.30 ? 1.0 ? 1.0 ? 1.1 ns t octt ctt 0 ? 0.6 ? 0.6 ? 0.6 ns t oagp agp 0 ? 0.9 ? 0.9 ? 1.0 ns notes: 1. output timing is measured at 1.4 v with 35 pf external capacitive load for lvttl. for other i/o standards and different loads, see ta bl e 1 and ta b l e 2 .
virtex ? 2.5 v field programmable gate arrays r module 3 of 4 www.xilinx.com ds003-3 (v2.5) april 2, 2001 10 1-800-255-7778 product specification calculation of t ioop as a function of capacitance t ioop is the propagation delay from the o input of the iob to the pad. the values for t ioop were based on the standard capacitive load (csl) for each i/o standard as listed in ta b l e 1 . for other capacitive loads, use the formulas below to calcu- late the corresponding t ioop . t ioop = t ioop + t opadjust + (c load ? c sl ) * fl where: t opadjust is reported above in the output delay adjustment section. c load is the capacitive load for the design. table 1: constants for calculating t ioop standard csl (pf) fl (ns/pf) lvttl fast slew rate, 2ma drive 35 0.41 lvttl fast slew rate, 4ma drive 35 0.20 lvttl fast slew rate, 6ma drive 35 0.13 lvttl fast slew rate, 8ma drive 35 0.079 lvttl fast slew rate, 12ma drive 35 0.044 lvttl fast slew rate, 16ma drive 35 0.043 lvttl fast slew rate, 24ma drive 35 0.033 lvttl slow slew rate, 2ma drive 35 0.41 lvttl slow slew rate, 4ma drive 35 0.20 lvttl slow slew rate, 6ma drive 35 0.100 lvttl slow slew rate, 8ma drive 35 0.086 lvttl slow slew rate, 12ma drive 35 0.058 lvttl slow slew rate, 16ma drive 35 0.050 lvttl slow slew rate, 24ma drive 35 0.048 lv c mo s2 3 5 0 . 04 1 pci 33mhz 5v 50 0.050 pci 33mhz 3.3 v 10 0.050 pci 66 mhz 3.3 v 10 0.033 gtl 0 0.014 gtl+ 0 0.017 hstl class i 20 0.022 hstl class iii 20 0.016 hstl class iv 20 0.014 sstl2 class i 30 0.028 sstl2 class ii 30 0.016 sstl3 class i 30 0.029 sstl3 class ii 30 0.016 ctt 20 0.035 agp 10 0.037 notes: 1. i/o parameter measurements are made with the capacitance values shown above. see xilinx application note xapp133 for appropriate terminations. 2. i/o standard measurements are reflected in the ibis model information except where the ibis format precludes it. ta b l e 2 : delay measurement methodology standard v l (1) v h (1) meas. point v ref typ (2) lv t t l 0 3 1 . 4 - lv c m o s 2 0 2 . 5 1 . 1 2 5 - pci33_5 per pci spec - pci33_3 per pci spec - pci66_3 per pci spec - gtl v ref ? 0.2 v ref +0.2 v ref 0.80 gtl+ v ref ? 0.2 v ref +0.2 v ref 1.0 hstl class i v ref ? 0.5 v ref +0.5 v ref 0.75 hstl class iii v ref ? 0.5 v ref +0.5 v ref 0.90 hstl class iv v ref ? 0.5 v ref +0.5 v ref 0.90 sstl3 i & ii v ref ? 1.0 v ref +1.0 v ref 1.5 sstl2 i & ii v ref ? 0.75 v ref +0.75 v ref 1.25 ctt v ref ? 0.2 v ref +0.2 v ref 1.5 agp v ref ? (0.2xv cco ) v ref + (0.2xv cco ) v ref per agp spec notes: 1. input waveform switches between v l and v h . 2. measurements are made at vref (typ), maximum, and minimum. worst-case values are reported. 3. i/o parameter measurements are made with the capacitance values shown in ta bl e 1 . see xilinx application note xapp133 for appropriate terminations. 4. i/o standard measurements are reflected in the ibis model information except where the ibis format precludes it.
virtex ? 2.5 v field programmable gate arrays r ds003-3 (v2.5) april 2, 2001 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 11 clock distribution guidelines clock distribution switching characteristics description device symbol speed grade units -6 -5 -4 global clock skew (1) global clock skew between iob flip-flops xcv50 t gskewiob 0.10 0.12 0.14 ns, max xcv100 0.12 0.13 0.15 ns, max xcv150 0.12 0.13 0.15 ns, max xcv200 0.13 0.14 0.16 ns, max xcv300 0.14 0.16 0.18 ns, max xcv400 0.13 0.13 0.14 ns, max xcv600 0.14 0.15 0.17 ns, max xcv800 0.16 0.17 0.20 ns, max xcv1000 0.20 0.23 0.25 ns, max notes: 1. these clock-skew delays are provided for guidance only. they reflect the delays encountered in a typical design under worst-c ase conditions. precise values for a particular design are provided by the timing analyzer. description symbol speed grade units min -6 -5 -4 gclk iob and buffer global clock pad to output. t gpio 0.33 0.7 0.8 0.9 ns, max global clock buffer i input to o output t gio 0.34 0.7 0.8 0.9 ns, max
virtex ? 2.5 v field programmable gate arrays r module 3 of 4 www.xilinx.com ds003-3 (v2.5) april 2, 2001 12 1-800-255-7778 product specification i/o standard global clock input adjustments description symbol standard (1) speed grade units min -6 -5 -4 data input delay adjustments standard-specific global clock input delay adjustments t gplvttl lv t t l 0 0 0 0 n s , max t gplvcmos 2 lv c m o s 2 ? 0.02 ? 0.04 ? 0.04 ? 0.05 ns, max t gppci33_3 pci, 33 mhz, 3.3 v ? 0.05 ? 0.11 ? 0.12 ? 0.14 ns, max t gppci33_5 pci, 33 mhz, 5.0 v 0.13 0.25 0.28 0.33 ns, max t gppci66_3 pci, 66 mhz, 3.3 v ? 0.05 ? 0.11 ? 0.12 ? 0.14 ns, max t gpgtl gtl 0.7 0.8 0.9 0.9 ns, max t gpgtlp gtl+ 0.7 0.8 0.8 0.8 ns, max t gphstl hstl 0.7 0.7 0.7 0.7 ns, max t gpsstl2 sstl2 0.6 0.52 0.51 0.50 ns, max t gpsstl3 sstl3 0.6 0.6 0.55 0.54 ns, max t gpctt ctt 0.7 0.7 0.7 0.7 ns, max t gpagp agp 0.6 0.54 0.53 0.52 ns, max notes: 1. input timing for gplvttl is measured at 1.4 v. for other i/o standards, see ta b l e 2 .
virtex ? 2.5 v field programmable gate arrays r ds003-3 (v2.5) april 2, 2001 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 13 clb switching characteristics delays originating at f/g inputs vary slightly according to the input used. the values listed below are worst-case. precise values are provided by the timing analyzer. description symbol speed grade units min -6 -5 -4 combinatorial delays 4-input function: f/g inputs to x/y outputs t ilo 0.29 0.6 0.7 0.8 ns, max 5-input function: f/g inputs to f5 output t if5 0.32 0.7 0.8 0.9 ns, max 5-input function: f/g inputs to x output t if5x 0.36 0.8 0.8 1.0 ns, max 6-input function: f/g inputs to y output via f6 mux t if6y 0.44 0.9 1.0 1.2 ns, max 6-input function: f5in input to y output t f5iny 0.17 0.32 0.36 0.42 ns, max incremental delay routing through transparent latch to xq/yq outputs t ifnctl 0.31 0.7 0.7 0.8 ns, max by input to yb output t byyb 0.27 0.53 0.6 0.7 ns, max sequential delays ff clock clk to xq/yq outputs t cko 0.54 1.1 1.2 1.4 ns, max latch clock clk to xq/yq outputs t cklo 0.6 1.2 1.4 1.6 ns, max setup and hold times before/after clock clk (1) setup time / hold time 4-input function: f/g inputs t ick /t cki 0.6 / 0 1.2 / 0 1.4 / 0 1.5 / 0 ns, min 5-input function: f/g inputs t if5ck /t ckif5 0.7 / 0 1.3 / 0 1.5 / 0 1.7 / 0 ns, min 6-input function: f5in input t f5inck /t ckf5in 0.46 / 0 1.0 / 0 1.1 / 0 1.2 / 0 ns, min 6-input function: f/g inputs via f6 mux t if6ck /t ckif6 0.8 / 0 1.5 / 0 1.7 / 0 1.9 / 0 ns, min bx/by inputs t dick /t ckdi 0.30 / 0 0.6 / 0 0.7 / 0 0.8 / 0 ns, min ce input t ceck /t ckce 0.37 / 0 0.8 / 0 0.9 / 0 1.0 / 0 ns, min sr/by inputs (synchronous) t rck t ckr 0.33 / 0 0.7 / 0 0.8 / 0 0.9 / 0 ns, min clock clk minimum pulse width, high t ch 0.8 1.5 1.7 2.0 ns, min minimum pulse width, low t cl 0.8 1.5 1.7 2.0 ns, min set/reset minimum pulse width, sr/by inputs t rpw 1.3 2.5 2.8 3.3 ns, min delay from sr/by inputs to xq/yq outputs (asynchronous) t rq 0.54 1.1 1.3 1.4 ns, max delay from gsr to xq/yq outputs t iogsrq 4.9 9.7 10.9 12.5 ns, max toggle frequency (mhz) (for export control) f tog (mhz) 625 333 294 250 mhz notes: 1. a zero "0" hold time listing indicates no hold time or a negative hold time. negative values cannot be guaranteed "best-case" , but if a "0" is listed, there is no positive hold time.
virtex ? 2.5 v field programmable gate arrays r module 3 of 4 www.xilinx.com ds003-3 (v2.5) april 2, 2001 14 1-800-255-7778 product specification clb arithmetic switching characteristics setup times not listed explicitly can be approximated by decreasing the combinatorial delays by the setup time adjustment listed. precise values are provided by the timing analyzer. description symbol speed grade units min -6 -5 -4 combinatorial delays f operand inputs to x via xor t opx 0.37 0.8 0.9 1.0 ns, max f operand input to xb output t opxb 0.54 1.1 1.3 1.4 ns, max f operand input to y via xor t opy 0.8 1.5 1.7 2.0 ns, max f operand input to yb output t opyb 0.8 1.5 1.7 2.0 ns, max f operand input to cout output t opcyf 0.6 1.2 1.3 1.5 ns, max g operand inputs to y via xor t opgy 0.46 1.0 1.1 1.2 ns, max g operand input to yb output t opgyb 0.8 1.6 1.8 2.1 ns, max g operand input to cout output t opcyg 0.7 1.3 1.4 1.6 ns, max bx initialization input to cout t bxcy 0.41 0.9 1.0 1.1 ns, max cin input to x output via xor t cinx 0.21 0.41 0.46 0.53 ns, max cin input to xb t cinxb 0.02 0.04 0.05 0.06 ns, max cin input to y via xor t ciny 0.23 0.46 0.52 0.6 ns, max cin input to yb t cinyb 0.23 0.45 0.51 0.6 ns, max cin input to cout output t byp 0.05 0.09 0.10 0.11 ns, max multiplier operation f1/2 operand inputs to xb output via and t fandxb 0.18 0.36 0.40 0.46 ns, max f1/2 operand inputs to yb output via and t fandyb 0.40 0.8 0.9 1.1 ns, max f1/2 operand inputs to cout output via and t fandcy 0.22 0.43 0.48 0.6 ns, max g1/2 operand inputs to yb output via and t gandyb 0.25 0.50 0.6 0.7 ns, max g1/2 operand inputs to cout output via and t gandcy 0.07 0.13 0.15 0.17 ns, max setup and hold times before/after clock clk (1) setup time / hold time cin input to ffx t cckx /t ckcx 0.50 / 0 1.0 / 0 1.2 / 0 1.3 / 0 ns, min cin input to ffy t ccky /t ckcy 0.53 / 0 1.1 / 0 1.2 / 0 1.4 / 0 ns, min notes: 1. a zero "0" hold time listing indicates no hold time or a negative hold time. negative values can not be guaranteed "best-case ", but if a "0" is listed, there is no positive hold time.
virtex ? 2.5 v field programmable gate arrays r ds003-3 (v2.5) april 2, 2001 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 15 clb selectram switching characteristics description symbol speed grade units min -6 -5 -4 sequential delays clock clk to x/y outputs (we active) 16 x 1 mode t shcko16 1.2 2.3 2.6 3.0 ns, max clock clk to x/y outputs (we active) 32 x 1 mode t shcko32 1.2 2.7 3.1 3.5 ns, max shift-register mode clock clk to x/y outputs t reg 1.2 3.7 4.1 4.7 ns, max setup and hold times before/after clock clk (1) setup time / hold time f/g address inputs t as /t ah 0.25 / 0 0.5 / 0 0.6 / 0 0.7 / 0 ns, min bx/by data inputs (din) t ds /t dh 0.34 / 0 0.7 / 0 0.8 / 0 0.9 / 0 ns, min ce input (we) t ws /t wh 0.38 / 0 0.8 / 0 0.9 / 0 1.0 / 0 ns, min shift-register mode bx/by data inputs (din) t shdick 0.34 0.7 0.8 0.9 ns, min ce input (ws) t shceck 0.38 0.8 0.9 1.0 ns, min clock clk minimum pulse width, high t wph 1.2 2.4 2.7 3.1 ns, min minimum pulse width, low t wpl 1.2 2.4 2.7 3.1 ns, min minimum clock period to meet address write cycle time t wc 2.4 4.8 5.4 6.2 ns, min shift-register mode minimum pulse width, high t srph 1.2 2.4 2.7 3.1 ns, min minimum pulse width, low t srpl 1.2 2.4 2.7 3.1 ns, min notes: 1. a zero "0" hold time listing indicates no hold time or a negative hold time. negative values can not be guaranteed "best-case ", but if a "0" is listed, there is no positive hold time.
virtex ? 2.5 v field programmable gate arrays r module 3 of 4 www.xilinx.com ds003-3 (v2.5) april 2, 2001 16 1-800-255-7778 product specification block ram switching characteristics tbuf switching characteristics jtag test access port switching characteristics description symbol speed grade units min-6-5-4 sequential delays clock clk to dout output t bcko 1.7 3.4 3.8 4.3 ns, max setup and hold times before/after clock clk (1) setup time / hold time addr inputs t back /t bcka 0.6 / 0 1.2 / 0 1.3 / 0 1.5 / 0 ns, min din inputs t bdck /t bckd 0.6 / 0 1.2 / 0 1.3 / 0 1.5 / 0 ns, min en input t beck /t bcke 1.3 / 0 2.6 / 0 3.0 / 0 3.4 / 0 ns, min rst input t brck /t bckr 1.3 / 0 2.5 / 0 2.7 / 0 3.2 / 0 ns, min wen input t bwck /t bckw 1.2 / 0 2.3 / 0 2.6 / 0 3.0 / 0 ns, min clock clk minimum pulse width, high t bpwh 0.8 1.5 1.7 2.0 ns, min minimum pulse width, low t bpwl 0.8 1.5 1.7 2.0 ns, min clka -> clkb setup time for different ports t bccs 3.0 3.5 4.0 ns, min notes: 1. a zero "0" hold time listing indicates no hold time or a negative hold time. negative values can not be guaranteed "best-case ", but if a "0" is listed, there is no positive hold time. description symbol speed grade units min -6 -5 -4 combinatorial delays in input to out output t io 0000ns, max tri input to out output high-impedance t off 0.05 0.09 0.10 0.11 ns, max tri input to valid data on out output t on 0.05 0.09 0.10 0.11 ns, max description symbol speed grade units -6 -5 -4 tms and tdi setup times before tck t ta p t c k 4.0 4.0 4.0 ns, min tms and tdi hold times after tck t tcktap 2.0 2.0 2.0 ns, min output delay from clock tck to output tdo t tcktdo 11.0 11.0 11.0 ns, max maximum tck clock frequency f tck 33 33 33 mhz, max
virtex ? 2.5 v field programmable gate arrays r ds003-3 (v2.5) april 2, 2001 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 17 virtex pin-to-pin output parameter guidelines testing of switching parameters is modeled after testing methods specified by mil-m-38510/605. all devices are 100% functionally tested. listed below are representative values for typical pin locations and normal clock loading. values are expressed in nanoseconds unless otherwise noted. global clock input to output delay for lvttl, 12 ma, fast slew rate, with dll global clock input-to-output delay for lvttl, 12 ma, fast slew rate, without dll description symbol device speed grade units min -6 -5 -4 lvttl global clock input to output delay using output flip-flop, 12 ma, fast slew rate, with dll. for data output with different standards, adjust delays with the values shown in output delay adjustments. t ickofdll xcv50 1.0 3.1 3.3 3.6 ns, max xcv100 1.0 3.1 3.3 3.6 ns, max xcv150 1.0 3.1 3.3 3.6 ns, max xcv200 1.0 3.1 3.3 3.6 ns, max xcv300 1.0 3.1 3.3 3.6 ns, max xcv400 1.0 3.1 3.3 3.6 ns, max xcv600 1.0 3.1 3.3 3.6 ns, max xcv800 1.0 3.1 3.3 3.6 ns, max xcv1000 1.0 3.1 3.3 3.6 ns, max notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. output timing is measured at 1.4 v with 35 pf external capacitive load for lvttl. the 35 pf load does not apply to the min va lues. for other i/o standards and different loads, see ta bl e 1 and ta bl e 2 . 3. dll output jitter is already included in the timing calculation. description symbol device speed grade units min -6 -5 -4 lvttl global clock input to output delay using output flip-flop, 12 ma, fast slew rate, without dll. for data output with different standards, adjust delays with the values shown in input and output delay adjustments. for i/o standards requiring v ref , such as gtl, gtl+, sstl, hstl, ctt, and ago, an additional 600 ps must be added. t ickof xcv50 1.5 4.6 5.1 5.7 ns, max xcv100 1.5 4.6 5.1 5.7 ns, max xcv150 1.5 4.7 5.2 5.8 ns, max xcv200 1.5 4.7 5.2 5.8 ns, max xcv300 1.5 4.7 5.2 5.9 ns, max xcv400 1.5 4.8 5.3 6.0 ns, max xcv600 1.6 4.9 5.4 6.0 ns, max xcv800 1.6 4.9 5.5 6.2 ns, max xcv1000 1.7 5.0 5.6 6.3 ns, max notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. output timing is measured at 1.4 v with 35 pf external capacitive load for lvttl. the 35 pf load does not apply to the min values. for other i/o standards and different loads, see ta bl e 1 and ta bl e 2 .
virtex ? 2.5 v field programmable gate arrays r module 3 of 4 www.xilinx.com ds003-3 (v2.5) april 2, 2001 18 1-800-255-7778 product specification minimum clock-to-out for virtex devices i/o standard with dll without dll all devices v50 v100 v150 v200 v300 v400 v600 v800 v1000 units *lvttl_s2 5.2 6.0 6.0 6.0 6.0 6.1 6.1 6.1 6.1 6.1 ns *lvttl_s4 3.5 4.3 4.3 4.3 4.3 4.4 4.4 4.4 4.4 4.4 ns *lvttl_s6 2.8 3.6 3.6 3.6 3.6 3.7 3.7 3.7 3.7 3.7 ns *lvttl_s8 2.2 3.1 3.1 3.1 3.1 3.1 3.1 3.2 3.2 3.2 ns *lvttl_s12 2.0 2.9 2.9 2.9 2.9 2.9 2.9 3.0 3.0 3.0 ns *lvttl_s16 1.9 2.8 2.8 2.8 2.8 2.8 2.8 2.9 2.9 2.9 ns *lvttl_s24 1.8 2.6 2.6 2.7 2.7 2.7 2.7 2.7 2.7 2.8 ns *lvttl_f2 2.9 3.8 3.8 3.8 3.8 3.8 3.8 3.9 3.9 3.9 ns *lvttl_f4 1.7 2.6 2.6 2.6 2.6 2.6 2.6 2.7 2.7 2.7 ns *lvttl_f6 1.2 2.0 2.0 2.0 2.1 2.1 2.1 2.1 2.1 2.2 ns *lvttl_f8 1.1 1.9 1.9 1.9 1.9 2.0 2.0 2.0 2.0 2.0 ns *lvttl_f12 1.0 1.8 1.8 1.8 1.8 1.9 1.9 1.9 1.9 1.9 ns *lvttl_f16 0.9 1.7 1.8 1.8 1.8 1.8 1.8 1.8 1.9 1.9 ns *lvttl_f24 0.9 1.7 1.7 1.7 1.8 1.8 1.8 1.8 1.8 1.9 ns lvcmos2 1.1 1.9 1.9 1.9 2.0 2.0 2.0 2.0 2.0 2.1 ns pci33_3 1.5 2.4 2.4 2.4 2.4 2.4 2.4 2.5 2.5 2.5 ns pci33_5 1.4 2.2 2.2 2.3 2.3 2.3 2.3 2.3 2.3 2.4 ns pci66_3 1.1 1.9 1.9 2.0 2.0 2.0 2.0 2.0 2.1 2.1 ns gtl 1.6 2.5 2.5 2.5 2.5 2.5 2.5 2.6 2.6 2.6 ns gtl+ 1.7 2.5 2.5 2.6 2.6 2.6 2.6 2.6 2.6 2.7 ns hstl i 1.1 1.9 1.9 1.9 1.9 2.0 2.0 2.0 2.0 2.0 ns hstl iii 0.9 1.7 1.7 1.8 1.8 1.8 1.8 1.8 1.8 1.9 ns hstl iv 0.8 1.6 1.6 1.6 1.7 1.7 1.7 1.7 1.7 1.8 ns sstl2 i 0.9 1.7 1.7 1.7 1.7 1.8 1.8 1.8 1.8 1.8 ns sstl2 ii 0.8 1.6 1.6 1.6 1.6 1.7 1.7 1.7 1.7 1.7 ns sstl3 i 0.8 1.6 1.7 1.7 1.7 1.7 1.7 1.7 1.8 1.8 ns sstl3 ii 0.7 1.5 1.5 1.6 1.6 1.6 1.6 1.6 1.6 1.7 ns ctt 1.0 1.8 1.8 1.8 1.9 1.9 1.9 1.9 1.9 2.0 ns agp 1.0 1.8 1.8 1.9 1.9 1.9 1.9 1.9 1.9 2.0 ns *s = slow slew rate, f = fast slew rate notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. input and output timing is measured at 1.4 v for lvttl. for other i/o standards, see ta bl e 2 . in all cases, an 8 pf external capacitive load is used.
virtex ? 2.5 v field programmable gate arrays r ds003-3 (v2.5) april 2, 2001 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 19 virtex pin-to-pin input parameter guidelines testing of switching parameters is modeled after testing methods specified by mil-m-38510/605. all devices are 100% functionally tested. listed below are representative values for typical pin locations and normal clock loading. values are expressed in nanoseconds unless otherwise noted global clock set-up and hold for lvttl standard, with dll description symbol device speed grade units min -6 -5 -4 input setup and hold time relative to global clock input signal for lvttl standard. for data input with different standards, adjust the setup time delay by the values shown in input delay adjustments. no delay global clock and iff, with dll t psdll /t phdll xcv50 0.40 / ? 0.4 1.7 / ? 0.4 1.8 / ? 0.4 2.1 / ? 0.4 ns, min xcv100 0.40 / ? 0.4 1.7 / ? 0.4 1.9 / ? 0.4 2.1 / ? 0.4 ns, min xcv150 0.40 / ? 0.4 1.7 / ? 0.4 1.9 / ? 0.4 2.1 / ? 0.4 ns, min xcv200 0.40 / ? 0.4 1.7 / ? 0.4 1.9 / ? 0.4 2.1 / ? 0.4 ns, min xcv300 0.40 / ? 0.4 1.7 / ? 0.4 1.9 / ? 0.4 2.1 / ? 0.4 ns, min xcv400 0.40 / ? 0.4 1.7 / ? 0.4 1.9 / ? 0.4 2.1 / ? 0.4 ns, min xcv600 0.40 / ? 0.4 1.7 / ? 0.4 1.9 / ? 0.4 2.1 / ? 0.4 ns, min xcv800 0.40 / ? 0.4 1.7 / ? 0.4 1.9 / ? 0.4 2.1 / ? 0.4 ns, min xcv1000 0.40 / ? 0.4 1.7 / ? 0.4 1.9 / ? 0.4 2.1 / ? 0.4 ns, min iff = input flip-flop or latch notes: 1. set-up time is measured relative to the global clock input signal with the fastest route and the lightest load. hold time is measured relative to the global clock input signal with the slowest route and heaviest load. 2. dll output jitter is already included in the timing calculation. 3. a zero "0" hold time listing indicates no hold time or a negative hold time. negative values can not be guaranteed "best-case ", but if a "0" is listed, there is no positive hold time.
virtex ? 2.5 v field programmable gate arrays r module 3 of 4 www.xilinx.com ds003-3 (v2.5) april 2, 2001 20 1-800-255-7778 product specification global clock set-up and hold for lvttl standard, without dll description symbol device speed grade units min -6 -5 -4 input setup and hold time relative to global clock input signal for lvttl standard. (2) for data input with different standards, adjust the setup time delay by the values shown in input delay adjustments. full delay global clock and iff, without dll t psfd /t phfd xcv50 0.6 / 0 2.3 / 0 2.6 / 0 2.9 / 0 ns, min xcv100 0.6 / 0 2.3 / 0 2.6 / 0 3.0 / 0 ns, min xcv150 0.6 / 0 2.4 / 0 2.7 / 0 3.1 / 0 ns, min xcv200 0.7 / 0 2.5 / 0 2.8 / 0 3.2 / 0 ns, min xcv300 0.7 / 0 2.5 / 0 2.8 / 0 3.2 / 0 ns, min xcv400 0.7 / 0 2.6 / 0 2.9 / 0 3.3 / 0 ns, min xcv600 0.7 / 0 2.6 / 0 2.9 / 0 3.3 / 0 ns, min xcv800 0.7 / 0 2.7 / 0 3.1 / 0 3.5 / 0 ns, min xcv1000 0.7 / 0 2.8 / 0 3.1 / 0 3.6 / 0 ns, min iff = input flip-flop or latch notes: notes: 1. set-up time is measured relative to the global clock input signal with the fastest route and the lightest load. hold time is measured relative to the global clock input signal with the slowest route and heaviest load. 2. a zero "0" hold time listing indicates no hold time or a negative hold time. negative values can not be guaranteed "best-case ", but if a "0" is listed, there is no positive hold time.
virtex ? 2.5 v field programmable gate arrays r ds003-3 (v2.5) april 2, 2001 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 21 dll timing parameters switching parameters testing is modeled after testing methods specified by mil-m-38510/605; all devices are 100 percent functionally tested. because of the difficulty in directly measuring many internal timing parameters, those parameters are derived from benchmark timing patterns. the following guidelines reflect worst-case values across the recommended operating conditions. dll clock tolerance, jitter, and phase information all dll output jitter and phase specifications determined through statistical measurement at the package pins using a clock mirror configuration and matched drivers. description symbol speed grade units -6 -5 -4 min max min max min max input clock frequency (clkdllhf) fclkinhf 60 200 60 180 60 180 mhz input clock frequency (clkdll) fclkinlf 25 100 25 90 25 90 mhz input clock pulse width (clkdllhf) t dllpwhf 2.0 - 2.4 - 2.4 - ns input clock pulse width (clkdll) t dllpwlf 2.5 - 3.0 3.0 - ns notes: 1. all specifications correspond to commercial operating temperatures (0 c to + 85 c). description symbol f clkin clkdllhf clkdll units min max min max input clock period tolerance t iptol - 1.0 - 1.0 ns input clock jitter tolerance (cycle to cycle) t ijitcc - 150 - 300 ps time required for dll to acquire lock t lock > 60 mhz - 20 - 20 m s 50 - 60 mhz - - - 25 m s 40 - 50 mhz - - - 50 m s 30 - 40 mhz - - - 90 m s 25 - 30 mhz - - - 120 m s output jitter (cycle-to-cycle) for any dll clock output (1) t ojitcc 60 60 ps phase offset between clkin and clko (2) t phio 100 100 ps phase offset between clock outputs on the dll (3) t phoo 140 140 ps maximum phase difference between clkin and clko (4) t phiom 160 160 ps maximum phase difference between clock outputs on the dll (5) t phoom 200 200 ps notes: 1. output jitter is cycle-to-cycle jitter measured on the dll output clock, excluding input clock jitter. 2. phase offset between clkin and clko is the worst-case fixed time difference between rising edges of clkin and clko, excluding output jitter and input clock jitter. 3. phase offset between clock outputs on the dll is the worst-case fixed time difference between rising edges of any two dll outputs, excluding output jitter and input clock jitter. 4. maximum phase difference between clkin an clko is the sum of output jitter and phase offset between clkin and clko, or the greatest difference between clkin and clko rising edges due to dll alone ( excluding input clock jitter). 5. maximum phase difference between clock outputs on the dll is the sum of output jitter and phase offset between any dll clock outputs, or the greatest difference between any two dll output rising edges sue to dll alone ( excluding input clock jitter). 6. all specifications correspond to commercial operating temperatures (0 c to +85 c).
virtex ? 2.5 v field programmable gate arrays r module 3 of 4 www.xilinx.com ds003-3 (v2.5) april 2, 2001 22 1-800-255-7778 product specification figure 1: frequency tolerance and clock jitter t clkin t clkin + t iptol period tolerance: the allowed input clock period change in nanoseconds. output jitter: the difference between an ideal reference clock edge and the actual design. _ ds003_20c_110399 i deal period actual period + jitter +/- jitter + maximum phase difference phase offset and maximum phase difference + phase offset
virtex ? 2.5 v field programmable gate arrays r ds003-3 (v2.5) april 2, 2001 www.xilinx.com module 3 of 4 product specification 1-800-255-7778 23 revision history virtex data sheet the virtex data sheet contains the following modules: ds003-1, virtex 2.5v fpgas: introduction and ordering information (module 1) ds003-2, virtex 2.5v fpgas: functional description (module 2) ds003-3, virtex 2.5v fpgas: dc and switching characteristics (module 3) ds003-4, virtex 2.5v fpgas: pinout tables (module 4) date version revision 11/98 1.0 initial xilinx release. 01/99 1.2 updated package drawings and specs. 02/99 1.3 update of package drawings, updated specifications. 05/99 1.4 addition of package drawings and specifications. 05/99 1.5 replaced fg 676 & fg680 package drawings. 07/99 1.6 changed boundary scan information and changed figure 11, boundary scan bit sequence. updated iob input & output delays. added capacitance info for different i/o standards. added 5 v tolerant information. added dll parameters and waveforms and new pin-to-pin input and output parameter tables for global clock input to output and setup and hold. changed configuration information including figures 12, 14, 17 & 19. added device-dependent listings for quiescent currents iccintq and iccoq. updated iob input and output delays based on default standard of lvttl, 12 ma, fast slew rate. added iob input switching characteristics standard adjustments. 09/99 1.7 speed grade update to preliminary status, power-on specification and clock-to-out minimums additions, "0" hold time listing explanation, quiescent current listing update, and figure 6 addra input label correction. added t ijitcc parameter, changed t ojit to t ophase . 01/00 1.8 update to speed.txt file 1.96. corrections for crs 111036,111137, 112697, 115479, 117153, 117154, and 117612. modified notes for recommended operating conditions (voltage and temperature). changed bank information for v cco in cs144 package on p.43. 01/00 1.9 updated dll jitter parameter table and waveforms, added delay measurement methodology table for different i/o standards, changed buffered hex line info and input/output timing measurement notes. 03/00 2.0 new tbcko values; corrected fg680 package connection drawing; new note about status of cclk pin after configuration. 05/00 2.1 modified "pins not listed ..." statement. speed grade update to final status. 05/00 2.2 modified table 18. 09/00 2.3 added xcv400 values to table under minimum clock-to-out for virtex devices . corrected units column in table under iob input switching characteristics . added values to table under clb selectram switching characteristics . 10/00 2.4 corrected pinout information for devices in the bg256, bg432, and bg560 packages in ta bl e 1 8 . corrected bg256 pin function diagram . 04/01 2.5 revised minimums for global clock set-up and hold for lvttl standard, with dll . converted file to modularized format. see the virtex data sheet section.
? 2001 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as listed a t http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. ds003-4 (v2.5) april 2, 2001 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 1 virtex pin definitions 0 virtex? 2.5 v field programmable gate arrays ds003-4 (v2.5) april 2, 2001 03 product specification table 1: special purpose pins pin name dedicated pin direction description gck0, gck1, gck2, gck3 yes input clock input pins that connect to global clock buffers. these pins become user inputs when not needed for clocks. m0, m1, m2 yes input mode pins are used to specify the configuration mode. cclk yes input or output the configuration clock i/o pin: it is an input for selectmap and slave-serial modes, and output in master-serial mode. after configuration, it is input only, logic level = don?t care. program yes input initiates a configuration sequence when asserted low. done yes bidirectional indicates that configuration loading is complete, and that the start-up sequence is in progress. the output can be open drain. init no bidirectional (open-drain) when low, indicates that the configuration memory is being cleared. the pin becomes a user i/o after configuration. busy/ dout no output in selectmap mode, busy controls the rate at which configuration data is loaded. the pin becomes a user i/o after configuration unless the selectmap port is retained. in bit-serial modes, dout provides header information to downstream devices in a daisy-chain. the pin becomes a user i/o after configuration. d0/din, d1, d2, d3, d4, d5, d6, d7 no input or output in selectmap mode, d0 - d7 are configuration data pins. these pins become user i/os after configuration unless the selectmap port is retained. in bit-serial modes, din is the single data input. this pin becomes a user i/o after configuration. write no input in selectmap mode, the active-low write enable signal. the pin becomes a user i/o after configuration unless the selectmap port is retained. cs no input in selectmap mode, the active-low chip select signal. the pin becomes a user i/o after configuration unless the selectmap port is retained. tdi, tdo, tms, tck yes mixed boundary-scan test-access-port pins, as defined in ieee 1149.1. dxn, dxp yes n/a temperature-sensing diode pins. (anode: dxp, cathode: dxn) v ccint yes input power-supply pins for the internal core logic. v cco yes input power-supply pins for the output drivers (subject to banking rules) v ref no input input threshold voltage pins. become user i/os when an external threshold voltage is not needed (subject to banking rules). gnd yes input ground r
virtex ? 2.5 v field programmable gate arrays r module 4 of 4 www.xilinx.com ds003-4 (v2.5) april 2, 2001 2 1-800-255-7778 product specification virtex pinout information pinout tables see the xilinx weblinx web site ( http://www.xilinx.com/partinfo/databook.htm ) for updates or additional pinout information. for convenience, ta b l e 2 , ta b l e 3 and ta b l e 4 list the locations of special-purpose and power-supply pins. pins not listed are either user i/os or not connected, depending on the device/package combination. see the pinout diagrams starting on page 17 for any pins not listed for a particular part/package combination. table 2: virtex pinout tables (chip-scale and qfp packages) pin name device cs144 tq144 pq/hq240 gck0 all k7 90 92 gck1 all m7 93 89 gck2 all a7 19 210 gck3 all a6 16 213 m0 all m1 110 60 m1 all l2 112 58 m2 all n2 108 62 cclk all b13 38 179 program all l12 72 122 done all m12 74 120 init all l13 71 123 busy/dout all c11 39 178 d0/din all c12 40 177 d1 all e10 45 167 d2 all e12 47 163 d3 all f11 51 156 d4 all h12 59 145 d5 all j13 63 138 d6 all j11 65 134 d7 all k10 70 124 write all c10 32 185 cs all d10 33 184 tdi all a11 34 183 tdo all a12 36 181 tms all b1 143 2 tck all c3 2 239 v ccint all a9, b6, c5, g3, g12, m5, m9, n6 10, 15, 25, 57, 84, 94, 99, 126 16, 32, 43, 77, 88, 104, 137, 148, 164, 198, 214, 225
virtex ? 2.5 v field programmable gate arrays r ds003-4 (v2.5) april 2, 2001 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 3 v cco all banks 0 and 1: a2, a13, d7 banks 2 and 3: b12, g11, m13 banks 4 and 5: n1, n7, n13 banks 6 and 7: b2, g2, m2 no i/o banks in this package: 1, 17, 37, 55, 73, 92, 109, 128 no i/o banks in this package: 15, 30, 44, 61, 76, 90, 105, 121, 136, 150, 165, 180, 197, 212, 226, 240 v ref , bank 0 (v ref pins are listed incrementally. connect all pins listed for both the required device and all smaller devices listed in the same package.) within each bank, if input reference voltage is not required, all v ref pins are general i/o. xcv50 c4, d6 5, 13 218, 232 xcv100/150 ... + b4 ... + 7 ... + 229 xcv200/300 ... + 236 xcv400 ... + 215 xcv600 ... + 230 xcv800 ... + 222 v ref , bank 1 (v ref pins are listed incrementally. connect all pins listed for both the required device and all smaller devices listed in the same package.) within each bank, if input reference voltage is not required, all v ref pins are general i/o. xcv50 a10, b8 22, 30 191, 205 xcv100/150 ... + d9 ... + 28 ... + 194 xcv200/300 ... + 187 xcv400 ... + 208 xcv600 ... + 193 xcv800 ... + 201 v ref , bank 2 (v ref pins are listed incrementally. connect all pins listed for both the required device and all smaller devices listed in the same package.) within each bank, if input reference voltage is not required, all v ref pins are general i/o. xcv50 d11, f10 42, 50 157, 171 xcv100/150 ... + d13 ... + 44 ... + 168 xcv200/300 ... + 175 xcv400 ... + 154 xcv600 ... + 169 xcv800 ... + 161 table 2: virtex pinout tables (chip-scale and qfp packages) (continued) pin name device cs144 tq144 pq/hq240
virtex ? 2.5 v field programmable gate arrays r module 4 of 4 www.xilinx.com ds003-4 (v2.5) april 2, 2001 4 1-800-255-7778 product specification v ref , bank 3 (v ref pins are listed incrementally. connect all pins listed for both the required device and all smaller devices listed in the same package.) within each bank, if input reference voltage is not required, all v ref pins are general i/o. xcv50 h11, k12 60, 68 130, 144 xcv100/150 ... + j10 ... + 66 ... + 133 xcv200/300 ... + 126 xcv400 ... + 147 xcv600 ... + 132 xcv800 ... + 140 v ref , bank 4 (v ref pins are listed incrementally. connect all pins listed for both the required device and all smaller devices listed in the same package.) within each bank, if input reference voltage is not required, all v ref pins are general i/o. xcv50 l8, l10 79, 87 97, 111 xcv100/150 ... + n10 ... + 81 ... + 108 xcv200/300 ... + 115 xcv400 ... + 94 xcv600 ... + 109 xcv800 ... + 101 v ref , bank 5 (v ref pins are listed incrementally. connect all pins listed for both the required device and all smaller devices listed in the same package.) within each bank, if input reference voltage is not required, all v ref pins are general i/o. xcv50 l4, l6 96, 104 70, 84 xcv100/150 ... + n4 ... + 102 ... + 73 xcv200/300 ... + 66 xcv400 ... + 87 xcv600 ... + 72 xcv800 ... + 80 table 2: virtex pinout tables (chip-scale and qfp packages) (continued) pin name device cs144 tq144 pq/hq240
virtex ? 2.5 v field programmable gate arrays r ds003-4 (v2.5) april 2, 2001 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 5 v ref , bank 6 (v ref pins are listed incrementally. connect all pins listed for both the required device and all smaller devices listed in the same package.) within each bank, if input reference voltage is not required, all v ref pins are general i/o. xcv50 h2, k1 116, 123 36, 50 xcv100/150 ... + j3 ... + 118 ... + 47 xcv200/300 ... + 54 xcv400 ... + 33 xcv600 ... + 48 xcv800 ... + 40 v ref , bank 7 (v ref pins are listed incrementally. connect all pins listed for both the required device and all smaller devices listed in the same package.) within each bank, if input reference voltage is not required, all v ref pins are general i/o. xcv50 d4, e1 133, 140 9, 23 xcv100/150 ... + d2 ... + 138 ... + 12 xcv200/300 ... + 5 xcv400 ... + 26 xcv600 ... + 11 xcv800 ... + 19 gnd all a1, b9, b11, c7, d5, e4, e11, f1, g10, j1, j12, l3, l5, l7, l9, n12 9, 18, 26, 35, 46, 54, 64 120, 129, 136, 144, 1, 8, 14, 22, 29, 37, 45, 51, 59, 69, 75, 83, 91, 98, 106, 112, 119, 129, 135, 143, 151, 158, 166, 172, 182, 190, 196, 204, 211, 219, 227, 233 table 2: virtex pinout tables (chip-scale and qfp packages) (continued) pin name device cs144 tq144 pq/hq240
virtex ? 2.5 v field programmable gate arrays r module 4 of 4 www.xilinx.com ds003-4 (v2.5) april 2, 2001 6 1-800-255-7778 product specification table 3: virtex pinout tables (bga) pin name device bg256 bg352 bg432 bg560 gck0 all y11 ae13 al16 al17 gck1 all y10 af14 ak16 aj17 gck2 all a10 b14 a16 d17 gck3 all b10 d14 d17 a17 m0 all y1 ad24 ah28 aj29 m1 all u3 ab23 ah29 ak30 m2 all w2 ac23 aj28 an32 cclk all b19 c3 d4 c4 program all y20 ac4 ah3 am1 done all w19 ad3 ah4 aj5 init all u18 ad2 aj2 ah5 busy/dout all d18 e4 d3 d4 d0/din all c19 d3 c2 e4 d1 all e20 g1 k4 k3 d2 all g19 j3 k2 l4 d3 all j19 m3 p4 p3 d4 all m19 r3 v4 w4 d5 all p19 u4 ab1 ab5 d6 all t20 v3 ab3 ac4 d7 all v19 ac3 ag4 aj4 write alla19d5b4d6 cs all b18 c4 d5 a2 tdi all c17 b3 b3 d5 tdo all a20 d4 c4 e6 tms all d3 d23 d29 b33 tck all a1 c24 d28 e29 dxn all w3 ad23 ah27 ak29 dxp all v4 ae24 ak29 aj28
virtex ? 2.5 v field programmable gate arrays r ds003-4 (v2.5) april 2, 2001 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 7 v ccint (v ccint pins are listed incrementally. connect all pins listed for both the required device and all smaller devices listed in the same package.) xcv50/100 c10, d6, d15, f4, f17, l3, l18, r4, r17, u6, u15, v10 xcv150/200/300 a20, c14, d10, j24, k4, p2, p25, v24, w2, ac10, ae14, b16, d12, l1, l25, r23, t1, af11, af16 a10, a17, b23, c14, c19, k3, k29, n2, n29, t1, t29, w2, w31, ab2, ab30, aj10, aj16, ak13, ak19, ak22, b26, c7, f1, f30, ae29, af1, ah8, ah24 xcv400/600 a21, b14, b18, b28, c24, e9, e12, f2, h30, j1, k32, n1, n33, u5, u30, y2, y31, ad2, ad32, ag3, ag31, ak8, ak11, ak17, ak20, al14, al27, an25, b12, c22, m3, n29, ab2, ab32, aj13, al22, xcv800/1000 v cco , bank 0 all d7, d8 a17, b25, d19 a21, c29, d21 a22, a26, a30, b19, b32 v cco , bank 1 all d13, d14 a10, d7, d13 a1, a11, d11 a10, a16, b13, c3, e5 v cco , bank 2 all g17, h17 b2, h4, k1 c3, l1, l4 b2, d1, h1, m1, r2 v cco , bank 3 all n17, p17 p4, u1, y4 aa1, aa4, aj3 v1, aa2, ad1, ak1, al2 v cco , bank 4 all u13, u14 ac8, ae2, af10 ah11, al1, al11 am2, am15, an4, an8, an12 v cco , bank 5 all u7, u8 ac14, ac20, af17 ah21, aj29, al21 al31, am21, an18, an24, an30 v cco , bank 6 all n4, p4 u26, w23, ae25 aa28, aa31, al31 w32, ab33, af33, ak33, am32 v cco , bank 7 all g4, h4 g23, k26, n23 a31, l28, l31 c32, d33, k33, n32, t33 table 3: virtex pinout tables (bga) (continued) pin name device bg256 bg352 bg432 bg560
virtex ? 2.5 v field programmable gate arrays r module 4 of 4 www.xilinx.com ds003-4 (v2.5) april 2, 2001 8 1-800-255-7778 product specification v ref , bank 0 (vref pins are listed incrementally. connect all pins listed for both the required device and all smaller devices listed in the same package.) within each bank, if input reference voltage is not required, all v ref pins are general i/o. xcv50 a8, b4 xcv100/150 ... + a4 a16,c19, c21 xcv200/300 ... + a2 ... + d21 b19, d22, d24, d26 xcv400 ... + b15 ... + c18 a19, d20, d26, e23, e27 xcv600 ... + c24 ... + e24 xcv800 ... + b21 ... + e21 xcv1000 ... + d29 v ref , bank 1 (vref pins are listed incrementally. connect all pins listed for both the required device and all smaller devices listed in the same package.) within each bank, if input reference voltage is not required, all v ref pins are general i/o. xcv50 a17, b12 xcv100/150 ... + b15 b6, c9, c12 xcv200/300 ... + b17 ... + d6 a13, b7, c6, c10 xcv400 ... + c13 ... + b15 a6, d7, d11, d16, e15 xcv600 ... + d10 ... + d10 xcv800 ... + b12 ... + d13 xcv1000 ... + e7 v ref , bank 2 (v ref pins are listed incrementally. connect all pins listed for both the required device and all smaller devices listed in the same package.) within each bank, if input reference voltage is not required, all v ref pins are general i/o. xcv50 c20, j18 xcv100/150 ... + f19 e2, h2, m4 xcv200/300 ... + g18 ... + d2 e2, g3, j2, n1 xcv400 ... + m1 ... + r3 g5, h4, l5, p4, r1 xcv600 ... + h1 ... + k5 xcv800 ... + m3 ... + n5 xcv1000 ... + b3 v ref , bank 3 (v ref pins are listed incrementally. connect all pins listed for both the required device and all smaller devices listed in the same package.) within each bank, if input reference voltage is not required, all v ref pins are general i/o. xcv50 m18, v20 xcv100/150 ... + r19 r4, v4, y3 xcv200/300 ... + p18 ... + ac2 v2, ab4, ad4, af3 xcv400 . + r1 ... + u2 v4, w5, ad3, ae5, ak2 xcv600 ... + ac3 ... + af1 xcv800 ... + y3 ... + aa4 xcv1000 ... + ah4 table 3: virtex pinout tables (bga) (continued) pin name device bg256 bg352 bg432 bg560
virtex ? 2.5 v field programmable gate arrays r ds003-4 (v2.5) april 2, 2001 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 9 v ref , bank 4 (v ref pins are listed incrementally. connect all pins listed for both the required device and all smaller devices listed in the same package.) within each bank, if input reference voltage is not required, all v ref pins are general i/o. xcv50 v12, y18 xcv100/150 ... + w15 ac12, ae5, ae8, xcv200/300 ... + v14 ... + ae4 aj7, al4, al8, al13 xcv400 ... + af12 ... + ak15 al7, al10, al16, am4, am14 xcv600 ... + ak8 ... + al9 xcv800 ... + aj12 ... + ak13 xcv1000 ... + an3 v ref , bank 5 (v ref pins are listed incrementally. connect all pins listed for both the required device and all smaller devices listed in the same package.) within each bank, if input reference voltage is not required, all v ref pins are general i/o. xcv50 v9, y3 xcv100/150 ... + w6 ac15, ac18, ad20 xcv200/300 ... + v7 ... + ae23 aj18, aj25, ak23, ak27 xcv400 ... + af15 ... + aj17 aj18, aj25, al20, al24, al29 xcv600 ... + al24 ... + am26 xcv800 ... + ah19 ... + an23 xcv1000 ... + ak28 v ref , bank 6 (v ref pins are listed incrementally. connect all pins listed for both the required device and all smaller devices listed in the same package.) within each bank, if input reference voltage is not required, all v ref pins are general i/o. xcv50 m2, r3 xcv100/150 ... + t1 r24, y26, aa25, xcv200/300 ... + t3 ... + ad26 v28, ab28, ae30, af28 xcv400 ... + p24 ... + u28 v29, y32, ad31, ae29, ak32 xcv600 ... + ac28 ... + ae31 xcv800 ... + y30 ... + aa30 xcv1000 ... + ah30 table 3: virtex pinout tables (bga) (continued) pin name device bg256 bg352 bg432 bg560
virtex ? 2.5 v field programmable gate arrays r module 4 of 4 www.xilinx.com ds003-4 (v2.5) april 2, 2001 10 1-800-255-7778 product specification v ref , bank 7 (v ref pins are listed incrementally. connect all pins listed for both the required device and all smaller devices listed in the same package.) within each bank, if input reference voltage is not required, all v ref pins are general i/o. xcv50 g3, h1 xcv100/150 ... + d1 d26, g26, l26 xcv200/300 ... + b2 ... + e24 f28, f31, j30, n30 xcv400 ... + m25 ... + r31 e31, g31, k31, p31, t31 xcv600 ... + j28 ... + h32 xcv800 ... + m28 ... + l33 xcv1000 ... + d31 gnd all c3, c18, d4, d5, d9, d10, d16, d17. e4, e17, j4, j17, k4, k17, l4, l17, m4, m17, t4, t17, u4, u5, u9, u10, u11, u12, u16, u17, v3, v18 a1, a2, a5, a8, a14, a19, a22, a25, a26, b1, b26, e1, e26, h1, h26, n1, p26, w1, w26, ab1, ab26, ae1, ae26, af1, af2, af5, af8, af13, af19, af22, af25, af26 a2, a3, a7, a9, a14, a18, a23, a25, a29, a30, b1, b2, b30, b31, c1, c31, d16, g1, g31, j1, j31, p1, p31, t4, t28, v1, v31, ac1, ac31, ae1, ae31, ah16, aj1, aj31, ak1, ak2, ak30, ak31, al2, al3, al7, al9 al14, al18 al23, al25, al29, al30 a1, a7, a12, a14, a18, a20, a24, a29, a32, a33, b1, b6, b9, b15, b23, b27, b31, c2, e1, f32, g2, g33, j32, k1, l2, m33, p1, p33, r32, t1, v33, w2, y1, y33, ab1, ac32, ad33, ae2, ag1, ag32, ah2, aj33, al32, am3, am7, am11, am19, am25, am28, am33, an1, an2, an5, an10, an14, an16, an20, an22, an27, an33 gnd (1) all j9, j10, j11, j12, k9, k10, k11, k12, l9, l10, l11, l12, m9, m10, m11, m12 no connect c31, ac2, ak4, al3 notes: 1. 16 extra balls (grounded) at package center. table 3: virtex pinout tables (bga) (continued) pin name device bg256 bg352 bg432 bg560
virtex ? 2.5 v field programmable gate arrays r ds003-4 (v2.5) april 2, 2001 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 11 table 4: virtex pinout tables (fine-pitch bga) pin name device fg256 fg456 fg676 fg680 gck0 all n8 w12 aa14 aw19 gck1 all r8 y11 ab13 au22 gck2 all c9 a11 c13 d21 gck3 all b8 c11 e13 a20 m0 all n3 ab2 ad4 at37 m1 all p2 u5 w7 au38 m2 all r3 y4 ab6 at35 cclk all d15 b22 d24 e4 program all p15 w20 aa22 at5 done all r14 y19 ab21 au5 init all n15 v19 y21 au2 busy/dout all c15 c21 e23 e3 d0/din all d14 d20 f22 c2 d1 all e16 h22 k24 p4 d2 all f15 h20 k22 p3 d3 all g16 k20 m22 r1 d4 all j16 n22 r24 ad3 d5 all m16 r21 u23 ag2 d6 all n16 t22 v24 ah1 d7 all n14 y21 ab23 ar4 write all c13 a20 c22 b4 cs all b13 c19 e21 d5 tdi all a15 b20 d22 b3 tdo all b14 a21 c23 c4 tms all d3 d3 f5 e36 tck all c4 c4 e6 c36 dxn all r4 y5 ab7 av37 dxp all p4 v6 y8 au35
virtex ? 2.5 v field programmable gate arrays r module 4 of 4 www.xilinx.com ds003-4 (v2.5) april 2, 2001 12 1-800-255-7778 product specification v ccint all c3, c14, d4, d13, e5, e12, m5, m12, n4, n13, p3, p14 e5, e18, f6, f17, g7, g8, g9, g14, g15, g16, h7, h16, j7, j16, p7, p16, r7, r16, t7, t8, t9, t14, t15, t16, u6, u17, v5, v18 g7, g20, h8, h19, j9, j10, j11, j16, j17, j18, k9, k18, l9, l18, t9, t18, u9, u18, v9, v10, v11, v16, v17, v18, w8, w19, y7, y20 ad5, ad35, ae5, ae35, al5, al35, am5, am35, ar8, ar9, ar15, ar16, ar24, ar25, ar31, ar32, e8, e9, e15, e16, e24, e25, e31, e32, h5, h35, j5, j35, r5, r35, t5, t35 v cco , bank 0 all e8, f8 f7, f8, f9, f10 g10, g11 h9, h10, h11, h12, j12, j13 e26, e27, e29, e30, e33, e34 v cco , bank 1 all e9, f9 f13, f14, f15, f16, g12, g13 h15, h16, h17, h18, j14, j15 e6, e7, e10, e11, e13, e14 v cco , bank 2 all h11, h12 g17, h17, j17, k16, k17, l16 j19, k19, l19, m18, m19, n18 f5, g5, k5, l5, n5, p5 v cco , bank 3 all j11, j12 m16, n16, n17, p17, r17, t17 p18, r18, r19, t19, u19, v19 af5, ag5, an5, ak5, aj5, ap5 v cco , bank 4 all l9. m9 t12, t13, u13, u14, u15, u16, v14, v15, w15, w16, w17, w18 ar6, ar7, ar10, ar11, ar13, ar14 v cco , bank 5 all l8, m8 t10, t11, u7, u8, u9, u10 v12, v13, w9,w10, w11, w12 ar26, ar27, ar29, ar30, ar33, ar34 v cco , bank 6 all j5, j6 m7, n6, n7, p6, r6, t6 p9, r8, r9, t8, u8, v8 af35, ag35, aj35, ak35, an35, ap35 v cco , bank 7 all h5, h6 g6, h6, j6, k6, k7, l7 j8, k8, l8, m8, m9, n9 f35, g35, k35, l35, n35, p35 v ref , bank 0 (vref pins are listed incrementally. connect all pins listed for both the required device and all smaller devices listed in the same package.) within each bank, if input reference voltage is not required, all v ref pins are general i/o. xcv50 b4, b7 xcv100/150 ... + c6 a9, c6, e8 xcv200/300 ... + a3 ... + b4 xcv400 a12, c11, d6, e8, g10 xcv600 ... + b7 a33, b28, b30, c23, c24, d33 xcv800 ... + b10 ... + a26 xcv1000 ... + d34 table 4: virtex pinout tables (fine-pitch bga) (continued) pin name device fg256 fg456 fg676 fg680
virtex ? 2.5 v field programmable gate arrays r ds003-4 (v2.5) april 2, 2001 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 13 v ref , bank 1 (vref pins are listed incrementally. connect all pins listed for both the required device and all smaller devices listed in the same package.) within each bank, if input reference voltage is not required, all v ref pins are general i/o. xcv50 b9, c11 xcv100/150 ... + e11 a18, b13, e14 xcv200/300 ... + a14 ... + a19 xcv400 a14, c20, c21, d15, g16 xcv600 ... + b19 b6, b8, b18, d11, d13, d17 xcv800 ... + a17 ... + b14 xcv1000 ... + b5 v ref , bank 2 (v ref pins are listed incrementally. connect all pins listed for both the required device and all smaller devices listed in the same package.) within each bank, if input reference voltage is not required, all v ref pins are general i/o. xcv50 f13, h13 xcv100/150 ... + f14 f21, h18, k21 xcv200/300 ... + e13 ... + d22 xcv400 f24, h23, k20, m23, m26 xcv600 ... + g26 g1, h4, j1, l2, v5, w3 xcv800 ... + k25 ... + n1 xcv1000 ... + d2 v ref , bank 3 (v ref pins are listed incrementally. connect all pins listed for both the required device and all smaller devices listed in the same package.) within each bank, if input reference voltage is not required, all v ref pins are general i/o. xcv50 k16, l14 xcv100/150 ... + l13 n21, r19, u21 xcv200/300 ... + m13 ... + u20 xcv400 r23, r25, u21, w22, w23 xcv600 ... + w26 ac1, aj2, ak3, al4, ar1, y1 xcv800 ... + u25 ... + af3 xcv1000 ... + ap4 table 4: virtex pinout tables (fine-pitch bga) (continued) pin name device fg256 fg456 fg676 fg680
virtex ? 2.5 v field programmable gate arrays r module 4 of 4 www.xilinx.com ds003-4 (v2.5) april 2, 2001 14 1-800-255-7778 product specification v ref , bank 4 (v ref pins are listed incrementally. connect all pins listed for both the required device and all smaller devices listed in the same package.) within each bank, if input reference voltage is not required, all v ref pins are general i/o. xcv50 p9, t12 xcv100/150 ... + t11 aa13, ab16, ab19 xcv200/300 ... + r13 ... + ab20 xcv400 ac15, ad18, ad21, ad22, af15 xcv600 ... + af20 at19, au7, au17, av8, av10, aw11 xcv800 ... + af17 ... + av14 xcv1000 ... + au6 v ref , bank 5 (v ref pins are listed incrementally. connect all pins listed for both the required device and all smaller devices listed in the same package.) within each bank, if input reference voltage is not required, all v ref pins are general i/o. xcv50 t4, p8 xcv100/150 ... + r5 w8, y10, aa5 xcv200/300 ... + t2 ... + y6 xcv400 aa10, ab8, ab12, ac7, af12 xcv600 ... + af8 at27, au29, au31, av35, aw21, aw23 xcv800 ... + ae10 ... + at25 xcv1000 ... + av36 v ref , bank 6 (v ref pins are listed incrementally. connect all pins listed for both the required device and all smaller devices listed in the same package.) within each bank, if input reference voltage is not required, all v ref pins are general i/o. xcv50 j3, n1 xcv100/150 ... + m1 n2, r4, t3 xcv200/300 ... + n2 ... + y1 xcv400 ab3, r1, r4, u6, v5 xcv600 ... + y1 ab35, ad37, ah39, ak39, am39, an36 xcv800 ... + u2 ... + ae39 xcv1000 ... + at39 table 4: virtex pinout tables (fine-pitch bga) (continued) pin name device fg256 fg456 fg676 fg680
virtex ? 2.5 v field programmable gate arrays r ds003-4 (v2.5) april 2, 2001 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 15 v ref , bank 7 (v ref pins are listed incrementally. connect all pins listed for both the required device and all smaller devices listed in the same package.) within each bank, if input reference voltage is not required, all v ref pins are general i/o. xcv50 c1, h3 xcv100/150 ... + d1 e2, h4, k3 xcv200/300 ... + b1 ... + d2 xcv400 f4, g4, k6, m2, m5 xcv600 ... + h1 e38, g38, l36, n36, u36, u38 xcv800 ... + k1 ... + n38 xcv1000 ... + f36 gnd all a1, a16, b2, b15, f6, f7, f10, f11, g6, g7, g8, g9, g10, g11, h7, h8, h9, h10, j7, j8, j9, j10, k6, k7, k8, k9, k10, k11, l6, l7, l10, l11, r2, r15, t1, t16 a1, a22, b2, b21, c3, c20, j9, j10, j11, j12, j13, j14, k9, k10, k11, k12, k13, k14, l9, l10, l11, l12, l13, l14, m9, m10, m11, m12, m13, m14, n9, n10, n11, n12, n13, n14, p9, p10, p11, p12, p13, p14, y3, y20, aa2, aa21, ab1, ab22 a1, a26, b2, b9, b14, b18, b25, c3, c24, d4, d23, e5, e22, j2, j25, k10, k11, k12, k13, k14, k15, k16, k17, l10, l11, l12, l13, l14, l15, l16, l17, m10, m11, m12, m13, m14, m15, m16, m17, n2, n10, n11, n12, n13, n14, n15, n16, n17, p10, p11, p12, p13, p14, p15, p16, p17, p25, r10, r11, r12, r13, r14, r15, r16, r17, t10, t11, t12, t13, t14, t15, t16, t17, u10, u11, u12, u13, u14, u15, u16, u17, v2, v25, ab5, ac4, ac23, ad3, ad24, ae2, ae9, ae13, ae18, ae25, af1, af26 a1, a2, a3, a37, a38, a39, aa5, aa35, ah4, ah5, ah35, ah36, ar5, ar12, ar19, ar20, ar21, ar28, ar35, at4, at12, at20, at28, at36, au1, au3, au20, au37, au39, av1, av2, av38, av39, aw1, aw2, aw3, aw37, aw38, aw39, b1, b2, b38, b39, c1, c3, c20, c37, c39, d4, d12, d20, d28, d36, e5, e12, e19, e20, e21, e28, e35, m4, m5, m35, m36, w5, w35, y3, y4, y5, y35, y36, y37 table 4: virtex pinout tables (fine-pitch bga) (continued) pin name device fg256 fg456 fg676 fg680
virtex ? 2.5 v field programmable gate arrays r module 4 of 4 www.xilinx.com ds003-4 (v2.5) april 2, 2001 16 1-800-255-7778 product specification no connect (no-connect pins are listed incrementally. all pins listed for both the required device and all larger devices listed in the same package are no connects.) xcv800 a2, a3, a15, a25, b1, b6, b11, b16, b21, b24, b26, c1, c2, c25, c26, f2, f6, f21, f25, l2, l25, n25, p2, t2, t25, aa2, aa6, aa21, aa25, ad1, ad2, ad25, ae1, ae3, ae6, ae11, ae14, ae16, ae21, ae24, ae26, af2, af24, af25 xcv600 ... xcv400 ... + a9, a10, a13, a16, a24, ac1, ac25, ae12, ae15, af3, af10, af11, af13, af14, af16, af18, af23, b4, b12, b13, b15, b17, d1, d25, h26, j1, k26, l1, m1, m25, n1, n26, p1, p26, r2, r26, t1, t26, u26, v1 xcv300 d4, d19, w4, w19 xcv200 ... + a2, a6, a12, b11, b16, c2, d1, d18, e17, e19, g2, g22, l2, l19, m2, m21, r3, r20, u3, u18, y22, aa1, aa3, aa11, aa16, ab7, ab12, ab21, ... xcv150 ... + a13, a14, c8, c9, e13, f11, h21, j1, j4, k2, k18, k19, m17, n1, p1, p5, p22, r22, w13, w15, aa9, aa10, ab8, ab14 table 4: virtex pinout tables (fine-pitch bga) (continued) pin name device fg256 fg456 fg676 fg680
virtex ? 2.5 v field programmable gate arrays r ds003-4 (v2.5) april 2, 2001 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 17 pinout diagrams the following diagrams, cs144 pin function diagram , page 17 through fg680 pin function diagram , page 27 , illustrate the locations of special-purpose pins on virtex fpgas. ta bl e 5 lists the symbols used in these diagrams. the diagrams also show i/o-bank boundaries. cs144 pin function diagram table 5: pinout diagram symbols symbol pin function ? general i/o ? device-dependent general i/o, n/c on smaller devices vv ccint v device-dependent v ccint , n/c on smaller devices ov cco rv ref r device-dependent v ref , remains i/o on smaller devices g ground ? , 1, 2, 3 global clocks ? , ? , ? m0, m1, m2 ? , ? , ? , ? , ? , ? , ? , ? d0/din, d1, d2, d3, d4, d5, d6, d7 b dout/busy ddone p program iinit k cclk wwrite scs t boundary-scan test access port + temperature diode, anode ? temperature diode, cathode n no connect ta b l e 5 : pinout diagram symbols (continued) symbol pin function figure 1: cs144 pin function diagram 1 2 3 4 5 6 7 9 10 11 12 13 8 1 ? cs144 (top view) 2 3 ? ? ? k p d i b ? ? ? ? ? ? ? ? w s t a ? ?? ??? ? ?? ? ?? ? ?? ? ? ?? ??? ?? ??? ?? ? ? ? ?? ? ? ? g ?? ???? 1 2 3 4 5 6 7 9 10 11 12 13 8 b c d e f g h j k l m n a b c d e f g h j k l m n t ? v ? o ? ? ? r ? ? ? ? ? g ? a b c d e f g h j k l m n ? ? ? ? t t v v vv vv v o o o o o ooo o o o r r r r rr r r r r r rr rr r r r r r r r gg g g gg g g gg ggg g r bank 0 bank 1 bank 5 bank 3 bank 4 bank 6 bank 2 bank 7
virtex ? 2.5 v field programmable gate arrays r module 4 of 4 www.xilinx.com ds003-4 (v2.5) april 2, 2001 18 1-800-255-7778 product specification tq144 pin function diagram figure 2: tq144 pin function diagram 1 2 3 4 5 6 7 9 10 11 12 13 14 15 16 17 19 20 21 22 23 24 25 26 27 29 30 31 32 33 34 35 36 8 18 28 37 39 40 41 42 43 44 45 46 47 49 50 51 52 53 54 55 56 57 59 60 61 62 63 64 65 66 38 48 58 67 69 70 71 72 68 73 74 75 76 77 79 80 81 82 83 84 85 86 87 89 90 91 92 93 94 95 96 78 88 97 99 100 98 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 119 120 121 122 123 124 125 126 127 129 130 131 132 133 134 135 136 118 128 137 139 140 141 142 143 144 138 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 ? ? ? ? ? ? ? ? ? ? ????????? ?????????? ?? ?? ? ????? ?? tq144 (top view) 2 3 ? ? ? kp d i b ? ? ? ? ? ? ? ? w s t t t t v v v v v v v v o o oo o o o o r r r r r rr rr r r r r r r r r g g g g gg g g g g g g g g g g r rr r r r r bank 0 bank 7 bank 6 bank 5 bank 1 bank 4 bank 2 bank 3
virtex ? 2.5 v field programmable gate arrays r ds003-4 (v2.5) april 2, 2001 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 19 pq240/hq240 pin function diagram figure 3: pq240/hq240 pin function diagram t o t ? ? r ? ? g r ? r r ? g o v ? ?? ? g r ? ? r v 3 o g 2 ? r ? ? r g ? ?? ? v o g ? r r ? r g ? ? r ? w s t g t ? ? r ? ? g r ? r r ? g o v ? ? ? ? g r ? ? r ? ? g o ? v r ? ? r g ? ? ? ? v o g ? r r ? r g ? ? r ? ? ? ? g ? o k b ? ? r ? ? g r ? r r ? g o v ? ? ? ? g r ? ? r ? ? g o ? v r ? ? r g ? ? ? ? v o g ? r r ? r g ? ? r ? ? i p o ? ? ? ? r ? ? g r ? r r ? g o v ? ?? ? g r ? ? r v 1 o g ? ? r ? ? r g ? ?? ? v o g ? r r ? r g ? ? r ? ? ? g d o 1 g 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 18 3 185 187 18 9 191 19 3 195 197 19 9 201 20 3 205 207 20 9 211 21 3 215 217 21 9 221 22 3 225 227 22 9 231 23 3 235 237 23 9 pq240/hq240 (top view) pins are shown staggered for readability bank 0 bank 7 bank 6 bank 5 bank 4 bank 3 bank 2 bank 1 r r r r r r r r
virtex ? 2.5 v field programmable gate arrays r module 4 of 4 www.xilinx.com ds003-4 (v2.5) april 2, 2001 20 1-800-255-7778 product specification bg256 pin function diagram figure 4: bg256 pin function diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 b c d e f g h j k l m n p r t u v w y a ? ? ? r ? ? ? ? ? b c d e f g h j k l m n p r t u v w y a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 bank 0 bank 1 bank 5 bank 3 bank 4 bank 6 bank 2 bank 7 bg256 (top view) r ? ??? ? ?????? ? ? r ? ????? ? ?? ? r ? ?? ?????? ?????? ??? ?? ?? ?? ?? r ??? r ??? ? ?? ???????? ??? ? ? ?????? ?????? ? ??? ??? ?? ?? ??? ??? ?? ?? ??? ??? ?? ? r ?? ?? r ? ??? ? ??? ?? ? ??? r ? ?? ?? tr2rwt r v rsk g 3 tg ? r tggvooggggoovggb gg ? vv ro o ? ro o g gggg gggg gggg gggg gr gg vg gv rg gr oo oo rv v gg ? ggvooggggoovgg i g+ rv r g r ? d r1 rp r r r r r rr ds003_18_100300
virtex ? 2.5 v field programmable gate arrays r ds003-4 (v2.5) april 2, 2001 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 21 bg352 pin function diagram figure 5: bg352 pin function diagram g 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af g ? ? g ? v g ? o r ? g ? ? ? o ? g ? ? g ? ? g g a g o ? ? ? ? ? ? ? ? v 2 ? ? ? ? ? ? ? r ? ? t o g ? ? t ? ? r ? r ? ? ? ? v r ? ? r ? ? ? ? s k ? ? r ? ? t ? r ? o ? ? ? ? 3 o v ? v ? ? o r t r ? ? ? ? ? ? ? o ? r ? ? r o ? r ? v ? o ? ? ? p ? r ? r ? ? ? ? r ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? d i ? g o + r ? ? ? v ? ? ? ? v ? ? ? ? ? r ? ? r r ? o g g g ? ? g ? ? g ? o v 1 g v o ? g ? ? g ? ? g g g ? r ? ? ? ? ? r ? ? o g ? ? ? ? ? v ? o ? ? ? r v ? ? ? ? ? ? ? ? o g v ? ? ? r v ? ? ? ? o ? ? ? ? ? v ? g ? ? o r ? ? ? ? r ? ? g ? ? ? b ? r g ? ? ? ? ? ? ? ? o ? r g ? ? ? ? v ? ? o ? ? ? v r ? ? ? ? ? g o ? v ? r ? ? ? ? ? v ? ? ? o r ? ? ? ? ? v g o r ? ? ? ? ? ? ? ? ? g ? b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 ? bank 1 bank 0 bank 4 bank 6 bank 5 bank 3 bank 7 bank 2 bg352 (top view) w ? ? ? ? ?? ? ? ds003_19_100600
virtex ? 2.5 v field programmable gate arrays r module 4 of 4 www.xilinx.com ds003-4 (v2.5) april 2, 2001 22 1-800-255-7778 product specification bg432 pin function diagram figure 6: bg432 pin function diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af a r b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 bank 1 bank 0 bank 4 bank 6 bank 5 bank 3 bank 7 bank 2 bg432 (top view) 27 28 29 30 31 27 28 29 30 31 ag ah aj ak al ag ah aj ak al ???? ? ? ??????? ?? ???? ?? ?? ???????? ? ?? ??? ??? ???? ???? ? ?? ???? ???? ??? ? ? ? ?? ?? ??? ?? ???? ?? ? ?? ?? ?? ??? ?? ? ??? ?????? ?? ? ????? ???? ? ?? ?? ??? ? ?? ?? ????? ??? ??? ?? ? ? ? ??? ?? ? ?? ?? ? ?? ?? ?? ? ?? ??? ? ??? ?? ? ?? ?? ??? ?? ? ? ? ??? ???? ? ??? ???? ? ??? ?? ??? ?? ??? ??? ?? ??? ?? ??? ?? ? ?? ?? ?? ???? ? ??? ???? r ro g v g r v1v gio o o r vr r + d gg g o gg g rg ? g og p gr g ? ? ? ? ? ? ? ? ? gr ? o r v g o ? g vr go g r o v r o o g r ogg g gvo rg 2 vg o g g g g o ggtw r r v g g got r r v v r og bks o g3 or r tt r rr gr g gr rg v oo oo rv vr g g vg gv gr ? rg v v v v v r r r r r r v rr r v v rr r v v r r rr r r rr r r r v g ds003_21_100300
virtex ? 2.5 v field programmable gate arrays r ds003-4 (v2.5) april 2, 2001 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 23 bg560 pin function diagram figure 7: bg560 pin function diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 k t ? ? i + ? o 1 ? b ? ? ? ? ? ? 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 ? bank 1 bank 0 bank 4 bank 6 bank 5 bank 3 bank 7 bank 2 bg560 (top view) w 27 28 29 30 31 32 33 27 28 29 30 31 32 33 b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af a ag ah aj ak al am an b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af a ag ah aj ak al am an ??? ????? ???? ? ?? ?? ?? ?? ??? ??? ?? ? ????????????????? ? ?????? ? ?? ?? ? ?? ?? ????? ?? ? ? ?? ? ?? ?? ????? ? ?? ? ? ? ? ??? ??????? ??? ?????? ?? ??? ? ??? ?? ? ??? ?? ??????? ? ? ???? ???? ???????? ? ?? ??? ?? ??? ? ??? ? ??? ????????? ???? ? ??? ??? ?? ? ???? ?? ?? ??? ??? ?? ??? ???? ???? ?? ? ?? ??? ??? ? ??? ? ?? ??? ???? ??? ?? ??? ? ?? ? ??? ??? ? ?? ???? ???? ?? ?? ? ??? ? ?? ? ? ??? ??? ??? ? ?? ? ??? ??? ??? ? ?? ??? ???? ?? ? ? ??? r o r o g o g g r g o g p r v v g r rv g g r r g r g n or o v r r v n r o g o o g g g o g o o v vg ov r og g ? o g g go v gv g v o r g g g r gs rg oggo3gg r v o g o go gg go g g v v ogvoggvgot go v n o otrr r2r r r o got r vvr r r v g gr rg or v v g g rv o gr o g v ov g ? rrg o r g g ro vv or r g gr o gv vrg d n v v v v v v v rr rr rr r r r r r r r r r r r r r r r r r ds003_22_100300
virtex ? 2.5 v field programmable gate arrays r module 4 of 4 www.xilinx.com ds003-4 (v2.5) april 2, 2001 24 1-800-255-7778 product specification fg256 pin function diagram figure 8: fg256 pin function diagram 3 1 ? fg256 (top view) 2 3 ? ? ? k p d i b ? ? ? ? ? ? ? ? w s t v o ? g ? ?????????? ? ?? ??? ? ?????? ? ? ???????? ? ???? ?? ? ?? ????? ? ? ????? ???? ?? ? ??? ?? ? ??? ????? ???? ????? ? ?? ??? ?? ?? ?? ??? ???? ? ??? ???? ? ? ?? ???? ? ? ?????? ??? 1 2 4 5 6 7 9 10 11 12 13 8 a b c d e f g h j k l m n p r t 16 14 15 1 2 3 4 5 6 7 9 10 11 12 13 8 16 14 15 a b c d e f g h j k l m n p r t t t t + v vv v v v v v v v v o oo oo oo oo oo oo oo r r r rr r r r r r r r r r r r r gg g g g g g gg g g gg g g gg g g gg g g gg g g gg g g gg gg r r r rr r r r r r r r r r r bank 0 bank 1 bank 5 bank 3 bank 4 bank 6 bank 2 bank 7
virtex ? 2.5 v field programmable gate arrays r ds003-4 (v2.5) april 2, 2001 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 25 fg456 pin function diagram notes: packages fg456 and fg676 are layout compatible. figure 9: fg456 pin function diagram 2 1 3 4 5 6 7 9 10 11 12 13 8 16 14 15 17 18 19 20 21 22 1 ? fg456 (top view) 2 3 ? ? ? k p d i b ? ? ? ? ? ? ? ? w s t v o r n ? g ???? ?? ? ????? ? ? ?????? ? ?? ??? ? ?? ? ???? ??????? ? ? ?????????? ??? ? ? ?? ?? ????? ? ? ???? ????? ?? ??? ? ????? ????? ??? ? ? ? ? ????? ????? ?? ?? ?? ? ?????? ?????? ?????? ?????? ? ??? ??? ????? ????? ??? ? ? ? ? ?? ?? ???? ???? ?? ?? ? ???? ??????????? ??? ??? ??? ??? ? ?????? ?? ? ??? ?????? ? ? ?? ??????? ?? ???? ? ???? ???????? ? ?? ? a b c d e f g h j k l m n p r t u v w y aa ab a b c d e f g h j k l m n p r t u v w y aa ab 1 2 3 4 5 6 7 9 10 11 12 13 8 16 14 15 17 18 19 20 21 22 t t t + v v v v v v vvv v v v v v v v vv v v v v v v v v v ooo oooo oooo oooo oooo oooo o o o oo o o o o o o o o o o o o o o o o o o o r r r r r r r r r r r r r r r r r r r r r r r r g gg g g g g gg g g gggggg gggggg gggggg gggggg gggggg gggggg n n n r r r r r r r ?? ?? bank 0 bank 1 bank 5 bank 3 bank 4 bank 6 bank 2 bank 7 ?
virtex ? 2.5 v field programmable gate arrays r module 4 of 4 www.xilinx.com ds003-4 (v2.5) april 2, 2001 26 1-800-255-7778 product specification fg676 pin function diagram notes: packages fg456 and fg676 are layout compatible. figure 10: fg676 pin function diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 agnn ???????? r ? rn ? r ??????? ng a bng ??? nr ? grn ?? g ? n ? gr ? n ?? ngn b cnng ??????? r ? 2 ?????? rrwtgn n c d ??? g ? r ???????? r ?????? tgk ?? d e ???? gt ? r ???? 3 ??????? sgb ??? e bank 7 f ? n ? rtn ?????????????? n ? ? rn ? f bank 2 g ??? r ?? v ? ? r ????? r ??? v ????? rg hr ?????? voooo ?? oooov ??? r ??? h j ? g ????? ovvvoooovvvo ????? g ? j kr ???? r ? ovggggggggvor ? ? ? ? r ? k l ? n ????? ovggggggggvo ????? n ? l m ? r ?? r ?? ooggggggggoo ?? ? r ?? rm n ? g ??? ??? oggggggggo ?????? n ? n p ? n ?????? oggggggggo ?????? g ? p rr ?? r ??? ooggggggggoo ??? r ? r ? r t ? n ????? ovggggggggvo ????? n ? t u ? r ??? r ? ovggggggggvo ? r ? ? ? r ? u v ? g ?? r ?? ov v voooov v vo ???? ? g ? v bank 6 w ?????? ? voooo ?? oooov ?? rr ?? r w bank 3 yr ????? v + ??????????? vi ????? y aa ? n ??? n ??? r ??? 0 ?????? np ?? n ? aa ab ?? r ? g ? r ??? r1 ??????? dg ? ??? ab ac ??? g ?? r ??????? r ??????? g ??? ac ad n n g ? ????????????? r ?? rr ? g n ? ad ae n g n ?? n ?? grn ? gn ? n ? g ?? n ?? ngn ae af g n ????? r ??? r ?? r ? r ?? r ??? nng af 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 bank 0 bank 1 bank 5 bank 4 fg676a - fg676 (top view)
virtex ? 2.5 v field programmable gate arrays r ds003-4 (v2.5) april 2, 2001 www.xilinx.com module 4 of 4 product specification 1-800-255-7778 27 fg680 pin function diagram figure 11: fg680 pin function diagram bank 1 bank 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 aggg ???????????????? 3 ????? r ?????? r ??? ggg a bggtwrr ? r ????? r ??? r ????????? r ? r ??????? gg b cg ? gt ??????????????? g ?? rr ??????????? tg ? gc d ? r ? gs ????? rgr ??? r ?? g2 ?????? g ???? rr ? g ??? d e ?? bkgoov voogoov v ?? ggg ?? v voogoov voogt ? r ? e bank 2 f ???? o or ??? f bank 7 gr ??? o o ?? r ? g h ??? rv v ???? h jr ??? v v ???? j k ???? o o ???? k l ? r ?? o or ??? l m ??? gg gg ??? m nr ??? o or ? r ? n p ?? ?? o o ???? p r ? ??? v v ???? r t ???? v v ???? t u ????? ? r ? r ? u v ???? r ????? v w ?? r ? g g ???? w yr ? ggg ggg ?? y aa ???? g g ???? aa ab ????? r ???? ab ac r ???? ????? ac ad ?? ? ? v v ? r ?? ad ae ???? v v ??? rae af ?? r ? o o ???? af ag ? ? ?? o o ???? ag ah ? ?? gg gg ?? rah aj ? r ?? o o ???? aj ak ?? r ? o o ??? rak al ??? rv v ???? al am ???? v v ??? ram an ???? o or ??? an bank 3 ap ??? ro o ???? ap bank 6 ar r ?? ? goov voogoov v ?? ggg ?? v voogoov voog ???? ar at ??? gp ?????? g ?????? rg ???? r ? rg ?????? ? g ? ? rat au g i g ? drr ????????? r ?? g ? 1 ?????? r ? r ??? + ? g ? gau av g g ????? r ? r ??? r ???????????????????? rr gg av aw ggg ??????? r ??????? 0 ? r ? r ????????????? ggg aw 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 bank 4 bank 5 fg680_12a - fg680 ( top view) bank 2 note : aa3, aa4, and ab2 are in bank 2 bank 7 note : aa37 is in bank 7
virtex ? 2.5 v field programmable gate arrays r module 4 of 4 www.xilinx.com ds003-4 (v2.5) april 2, 2001 28 1-800-255-7778 product specification revision history virtex data sheet the virtex data sheet contains the following modules: ds003-1, virtex 2.5v fpgas: introduction and ordering information (module 1) ds003-2, virtex 2.5v fpgas: functional description (module 2) ds003-3, virtex 2.5v fpgas: dc and switching characteristics (module 3) ds003-4, virtex 2.5v fpgas: pinout tables (module 4) date version revision 11/98 1.0 initial xilinx release. 01/99 1.2 updated package drawings and specs. 02/99 1.3 update of package drawings, updated specifications. 05/99 1.4 addition of package drawings and specifications. 05/99 1.5 replaced fg 676 & fg680 package drawings. 07/99 1.6 changed boundary scan information and changed figure 11, boundary scan bit sequence. updated iob input & output delays. added capacitance info for different i/o standards. added 5 v tolerant information. added dll parameters and waveforms and new pin-to-pin input and output parameter tables for global clock input to output and setup and hold. changed configuration information including figures 12, 14, 17 & 19. added device-dependent listings for quiescent currents iccintq and iccoq. updated iob input and output delays based on default standard of lvttl, 12 ma, fast slew rate. added iob input switching characteristics standard adjustments. 09/99 1.7 speed grade update to preliminary status, power-on specification and clock-to-out minimums additions, "0" hold time listing explanation, quiescent current listing update, and figure 6 addra input label correction. added t ijitcc parameter, changed t ojit to t ophase . 01/00 1.8 update to speed.txt file 1.96. corrections for crs 111036,111137, 112697, 115479, 117153, 117154, and 117612. modified notes for recommended operating conditions (voltage and temperature). changed bank information for v cco in cs144 package on p.43. 01/00 1.9 updated dll jitter parameter table and waveforms, added delay measurement methodology table for different i/o standards, changed buffered hex line info and input/output timing measurement notes. 03/00 2.0 new tbcko values; corrected fg680 package connection drawing; new note about status of cclk pin after configuration. 05/00 2.1 modified "pins not listed ..." statement. speed grade update to final status. 05/00 2.2 modified table 18. 09/00 2.3 added xcv400 values to table under minimum clock-to-out for virtex devices . corrected units column in table under iob input switching characteristics . added values to table under clb selectram switching characteristics . 10/00 2.4 corrected pinout information for devices in the bg256, bg432, and bg560 packages in ta bl e 1 8 . corrected bg256 pin function diagram . 04/01 2.5 revised minimums for global clock set-up and hold for lvttl standard, with dll . converted file to modularized format. see section virtex data sheet , below.

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